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Searched refs:MIU0_RQ4_MASK_L (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/mvd_v3/
H A DregMVD_EX.h131 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/mvd_v3/
H A DregMVD_EX.h131 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/mvd_v3/
H A DregMVD_EX.h131 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/mvd_v3/
H A DregMVD_EX.h132 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
H A DhalMVD_EX.c1055 HAL_MVD_RegWriteBit(MIU0_RQ4_MASK_L, bEnMask, BIT6); //MVD TLB Mheg Codec in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/mvd_lite/
H A DregMVD_EX.h131 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2+((0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/mvd_v3/
H A DregMVD_EX.h133 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/mvd_v3/
H A DregMVD_EX.h133 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/mvd_v3/
H A DregMVD_EX.h133 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/mvd_v3/
H A DregMVD_EX.h133 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/mvd_v3/
H A DregMVD_EX.h133 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) macro