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Searched refs:MIU0_REG_BASE (Results 1 – 25 of 93) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/mvd_lite/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
123 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
124 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
125 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
126 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
127 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
128 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
129 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
130 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
137 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0) //0x78<<1
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
123 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
124 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
125 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
126 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
127 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
128 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
129 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
130 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
133 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
123 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
124 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
125 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
126 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
127 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
128 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
129 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
130 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
133 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
123 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
124 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
125 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
126 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
127 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
128 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
129 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
130 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
133 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200 macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/mainz/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/mvd_v3/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200 macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/messi/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200UL macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/mvd/
H A DregMVD.h114 #define MIU0_REG_BASE 0x1200 macro
122 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
123 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
124 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
125 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
126 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
127 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
128 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
129 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
130 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/mvd_ex/
H A DregMVD_EX.h113 #define MIU0_REG_BASE 0x1200 macro
121 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2)
122 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1)
123 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2)
124 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1)
125 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2)
126 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1)
127 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2)
128 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1)
129 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0)
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