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Searched refs:MDrv_Write2ByteMask (Results 1 – 25 of 69) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_offline.c254 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
255 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
273 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
274 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
300 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
301 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_offline.c260 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
306 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_offline.c254 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
255 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
273 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
274 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
300 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
301 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_offline.c260 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
306 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
H A Dmhal_frc.c796 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
797 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
798 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
799 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
801 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
802 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
803 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
804 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
1469 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0101, 0x0101); // YUV in in MHal_FRC_Init()
1484 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0000, 0x0101); // RGB in in MHal_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_offline.c260 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
306 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
H A Dmhal_frc.c618 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
619 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
620 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
621 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
623 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
624 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
625 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
626 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
1165 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0101, 0x0101); in MHal_FRC_Init()
1387 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0101, 0x0101); // YUV in in MHal_FRC_Set_3D_QMap()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_offline.c260 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
306 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
H A Dmhal_frc.c757 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
758 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
759 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
760 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
762 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
763 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
764 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
765 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
1783 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0101, 0x0101); // YUV in in MHal_FRC_Init()
1808 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0000, 0x0101); // RGB in in MHal_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_offline.c260 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
306 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
H A Dmhal_frc.c779 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
780 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
781 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
782 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
784 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
785 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
786 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
787 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
1452 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0101, 0x0101); // YUV in in MHal_FRC_Init()
1467 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0000, 0x0101); // RGB in in MHal_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_offline.c260 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
306 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
H A Dmhal_frc.c757 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
758 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
759 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
760 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
762 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
763 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
764 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
765 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
1783 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0101, 0x0101); // YUV in in MHal_FRC_Init()
1808 MDrv_Write2ByteMask( REG_FRC_BK31B_10, 0x0000, 0x0101); // RGB in in MHal_FRC_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_offline.c260 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
278 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
303 MDrv_Write2ByteMask(REG_ADC_ATOP_5E_L, 0, 0x3fc); in Hal_XC_SetOffLineToHv()
304 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/ve/hal/mainz/ve/
H A Dmhal_tvencoder.c328 MDrv_Write2ByteMask(L_BK_VE_SRC(0x7D),BIT(14),BIT(14)); // mode for trigger TVE in Hal_VE_init()
329 MDrv_Write2ByteMask(L_BK_VE_ENC(0x3F),BIT(10),BIT(10)); // always do sync with TVE source in Hal_VE_init()
741 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),u16init_factor,0x7FF); in Hal_VE_set_v_initfactor()
742 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),BIT(15),BIT(15)); in Hal_VE_set_v_initfactor()
927 MDrv_Write2ByteMask(REG_SC_BK20_03_L, 0x0002, 0x0002); // set source from main in Hal_VE_set_mux()
928 MDrv_Write2ByteMask(REG_SC_BK57_2F_L, 0x0000, 0x8000); // set source from DI in Hal_VE_set_mux()
929 MDrv_Write2ByteMask(REG_SC_BK57_7F_L, 0x6000, 0x6000); // set 422 to 444 in Hal_VE_set_mux()
/utopia/UTPA2-700.0.x/modules/ve/hal/messi/ve/
H A Dmhal_tvencoder.c328 MDrv_Write2ByteMask(L_BK_VE_SRC(0x7D),BIT(14),BIT(14)); // mode for trigger TVE in Hal_VE_init()
329 MDrv_Write2ByteMask(L_BK_VE_ENC(0x3F),BIT(10),BIT(10)); // always do sync with TVE source in Hal_VE_init()
741 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),u16init_factor,0x7FF); in Hal_VE_set_v_initfactor()
742 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),BIT(15),BIT(15)); in Hal_VE_set_v_initfactor()
927 MDrv_Write2ByteMask(REG_SC_BK20_03_L, 0x0002, 0x0002); // set source from main in Hal_VE_set_mux()
928 MDrv_Write2ByteMask(REG_SC_BK57_2F_L, 0x0000, 0x8000); // set source from DI in Hal_VE_set_mux()
929 MDrv_Write2ByteMask(REG_SC_BK57_7F_L, 0x6000, 0x6000); // set 422 to 444 in Hal_VE_set_mux()
/utopia/UTPA2-700.0.x/modules/ve/hal/macan/ve/
H A Dmhal_tvencoder.c330 MDrv_Write2ByteMask(L_BK_VE_SRC(0x7D),BIT(14),BIT(14)); // mode for trigger TVE in Hal_VE_init()
331 MDrv_Write2ByteMask(L_BK_VE_ENC(0x3F),BIT(10),BIT(10)); // always do sync with TVE source in Hal_VE_init()
743 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),u16init_factor,0x7FF); in Hal_VE_set_v_initfactor()
744 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),BIT(15),BIT(15)); in Hal_VE_set_v_initfactor()
1695 MDrv_Write2ByteMask(L_BK_VE_SRC(0x1A), BIT(14) , BIT(14)); //H mirror in Hal_VE_Set_Mirror_Mode()
1700 MDrv_Write2ByteMask(L_BK_VE_SRC(0x1A), BIT(15) , BIT(15)); //V mirror in Hal_VE_Set_Mirror_Mode()
1705 MDrv_Write2ByteMask(L_BK_VE_SRC(0x1A), 0 , (BIT(15)| BIT(14))); //Non mirror in Hal_VE_Set_Mirror_Mode()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_offline.c236 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
254 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_offline.c236 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
254 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToSog_YUV()
280 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/ve/hal/mustang/ve/
H A Dmhal_tvencoder.c325 MDrv_Write2ByteMask(L_BK_VE_SRC(0x7D),BIT(14),BIT(14)); // mode for trigger TVE in Hal_VE_init()
326 MDrv_Write2ByteMask(L_BK_VE_ENC(0x3F),BIT(10),BIT(10)); // always do sync with TVE source in Hal_VE_init()
733 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),u16init_factor,0x7FF); in Hal_VE_set_v_initfactor()
734 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),BIT(15),BIT(15)); in Hal_VE_set_v_initfactor()
/utopia/UTPA2-700.0.x/modules/ve/hal/maldives/ve/
H A Dmhal_tvencoder.c325 MDrv_Write2ByteMask(L_BK_VE_SRC(0x7D),BIT(14),BIT(14)); // mode for trigger TVE in Hal_VE_init()
326 MDrv_Write2ByteMask(L_BK_VE_ENC(0x3F),BIT(10),BIT(10)); // always do sync with TVE source in Hal_VE_init()
730 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),u16init_factor,0x7FF); in Hal_VE_set_v_initfactor()
731 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),BIT(15),BIT(15)); in Hal_VE_set_v_initfactor()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c1660 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x80), stCropInfo.u16XStart, 0x1fff); in Hal_SC_sw_db()
1661 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x82), stCropInfo.u16YStart, 0x1fff); in Hal_SC_sw_db()
1662 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x84), stCropInfo.u16XSize, 0x1fff); in Hal_SC_sw_db()
1663 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x86), stCropInfo.u16YSize, 0x1fff); in Hal_SC_sw_db()
2329 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC0_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2330 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC0_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2331 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC0_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2332 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC0_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
2334 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC0_G0REQUEST_MASK, MIU_SC0_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2335 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC0_G1REQUEST_MASK, MIU_SC0_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c1573 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x80), stCropInfo.u16XStart, 0x1fff); in Hal_SC_sw_db()
1574 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x82), stCropInfo.u16YStart, 0x1fff); in Hal_SC_sw_db()
1575 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x84), stCropInfo.u16XSize, 0x1fff); in Hal_SC_sw_db()
1576 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x86), stCropInfo.u16YSize, 0x1fff); in Hal_SC_sw_db()
2242 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC0_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2243 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC0_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2244 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC0_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2245 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC0_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
2247 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC0_G0REQUEST_MASK, MIU_SC0_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2248 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC0_G1REQUEST_MASK, MIU_SC0_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_sc.c1656 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x80), stCropInfo.u16XStart, 0x1fff); in Hal_SC_sw_db()
1657 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x82), stCropInfo.u16YStart, 0x1fff); in Hal_SC_sw_db()
1658 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x84), stCropInfo.u16XSize, 0x1fff); in Hal_SC_sw_db()
1659 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x86), stCropInfo.u16YSize, 0x1fff); in Hal_SC_sw_db()
2339 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC0_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2340 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC0_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2341 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC0_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2342 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC0_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
2344 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC0_G0REQUEST_MASK, MIU_SC0_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2345 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC0_G1REQUEST_MASK, MIU_SC0_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/maxim/ve/
H A Dmhal_tvencoder.c338 MDrv_Write2ByteMask(L_BK_VE_SRC(0x7D),BIT(14),BIT(14)); // mode for trigger TVE in Hal_VE_init()
339 MDrv_Write2ByteMask(L_BK_VE_ENC(0x3F),BIT(10),BIT(10)); // always do sync with TVE source in Hal_VE_init()
751 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),u16init_factor,0x7FF); in Hal_VE_set_v_initfactor()
752 MDrv_Write2ByteMask(L_BK_VE_SRC(0x19),BIT(15),BIT(15)); in Hal_VE_set_v_initfactor()

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