Home
last modified time | relevance | path

Searched refs:L_BK_DLC (Results 1 – 25 of 49) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/dlc/hal/maldives/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h132 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
138 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
178 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
180 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
182 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
184 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
186 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
187 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
189 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
191 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/hal/mustang/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h132 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
138 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
178 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
180 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
182 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
184 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
186 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
187 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
189 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
191 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/maxim/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
141 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
181 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
183 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
185 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
187 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
189 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
190 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
192 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/macan/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
141 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
181 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
183 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
185 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
187 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
189 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
190 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
192 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/hal/mainz/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
141 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
181 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
183 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
185 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
187 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
189 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
190 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
192 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/mooney/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
141 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
181 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
183 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
185 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
187 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
189 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
190 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
192 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/messi/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
141 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
181 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
183 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
185 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
187 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
189 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
190 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
192 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
141 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
181 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
183 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
185 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
187 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
189 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
190 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
192 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7621/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
141 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
181 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
183 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
185 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
187 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
189 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
190 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
192 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
138 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
180 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
182 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
184 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
186 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
188 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
189 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
191 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
193 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
138 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
180 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
182 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
184 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
186 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
188 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
189 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
191 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
193 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/kano/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
138 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
180 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
182 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
184 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
186 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
188 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
189 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
191 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
193 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6lite/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x) macro
138 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
180 #define REG_ADDR_HISTOGRAM_RANGE_M_HST L_BK_DLC(0x1A)
182 #define REG_ADDR_HISTOGRAM_RANGE_M_VST L_BK_DLC(0x01)
184 #define REG_ADDR_HISTOGRAM_RANGE_S_HST L_BK_DLC(0x1B)
186 #define REG_ADDR_HISTOGRAM_RANGE_S_VST L_BK_DLC(0x03)
188 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
189 #define REG_ADDR_HISTOGRAM_TOTAL_SUM_L L_BK_DLC(0x06)
191 #define REG_ADDR_HISTOGRAM_TOTAL_COUNT_L L_BK_DLC(0x07)
193 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h137 #define L_BK_DLC(_x_) (REG_SCALER_FSC_BASE | (REG_SC_BK_DLC << 8) | (_x_ … macro
193 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
195 #define REG_ADDR_HISTOGRAM_8_RANGE_START L_BK_DLC(0x1C)
196 #define REG_ADDR_BLE_UPPER_BOND L_BK_DLC(0x09)
198 #define REG_ADDR_WLE_UPPER_BOND L_BK_DLC(0x0A)
200 #define REG_ADDR_MAIN_MAX_VALUE L_BK_DLC(0x0B)
202 #define REG_ADDR_DLC_DATA_START_MAIN L_BK_DLC(0x30)
203 #define REG_ADDR_DLC_DATA_EXTEND_N0_MAIN L_BK_DLC(0x76)
204 #define REG_ADDR_DLC_DATA_EXTEND_16_MAIN L_BK_DLC(0x77)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)
/utopia/UTPA2-700.0.x/modules/dlc/hal/maserati/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h137 #define L_BK_DLC(_x_) (REG_SCALER_FSC_BASE | (REG_SC_BK_DLC << 8) | (_x_ … macro
193 #define REG_ADDR_DLC_HANDSHAKE L_BK_DLC(0x04)
194 #define REG_ADDR_HISTOGRAM_RANGE_ENABLE L_BK_DLC(0x08)
195 #define REG_ADDR_HISTOGRAM_8_RANGE_START L_BK_DLC(0x1C)
196 #define REG_ADDR_BLE_UPPER_BOND L_BK_DLC(0x09)
198 #define REG_ADDR_WLE_UPPER_BOND L_BK_DLC(0x0A)
200 #define REG_ADDR_MAIN_MAX_VALUE L_BK_DLC(0x0B)
202 #define REG_ADDR_DLC_DATA_START_MAIN L_BK_DLC(0x30)
203 #define REG_ADDR_DLC_DATA_EXTEND_N0_MAIN L_BK_DLC(0x76)
204 #define REG_ADDR_DLC_DATA_EXTEND_16_MAIN L_BK_DLC(0x77)
[all …]
H A DMsDBC_LIB_Group_DTV2.h131 #define L_BK_DLC(x) BK_REG_L(BK_SCALER_BASE,x) macro
158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit)

12