| /utopia/UTPA2-700.0.x/modules/flash/hal/maldives/flash/serial/ |
| H A D | regSERFLASH.h | 166 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 291 {CFG_REG_READ, {0, ISP_SPI_CMD_RDSCUR, NULL, 0, 0, 1}},
4043 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
5396 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SERFLASH_ReadSecureReg()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/manhattan/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| /utopia/UTPA2-700.0.x/modules/flash/hal/macan/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| /utopia/UTPA2-700.0.x/modules/flash/hal/messi/flash/serial/ |
| H A D | regSERFLASH.h | 169 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| /utopia/UTPA2-700.0.x/modules/flash/hal/maxim/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| /utopia/UTPA2-700.0.x/modules/flash/hal/maserati/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 3881 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/M7821/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| /utopia/UTPA2-700.0.x/modules/flash/hal/M7621/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 3881 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/mainz/flash/serial/ |
| H A D | regSERFLASH.h | 169 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 3854 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/mooney/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 3844 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/k6lite/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 308 {CFG_REG_READ, {0, ISP_SPI_CMD_RDSCUR, NULL, 0, 0, 1}},
3650 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
5083 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SERFLASH_ReadSecureReg()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/kano/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 308 {CFG_REG_READ, {0, ISP_SPI_CMD_RDSCUR, NULL, 0, 0, 1}},
3630 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
5063 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SERFLASH_ReadSecureReg()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/curry/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 310 {CFG_REG_READ, {0, ISP_SPI_CMD_RDSCUR, NULL, 0, 0, 1}},
3644 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
5077 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SERFLASH_ReadSecureReg()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/k6/flash/serial/ |
| H A D | regSERFLASH.h | 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 308 {CFG_REG_READ, {0, ISP_SPI_CMD_RDSCUR, NULL, 0, 0, 1}},
3630 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
5063 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SERFLASH_ReadSecureReg()
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| /utopia/UTPA2-700.0.x/modules/flash/hal/mustang/flash/serial/ |
| H A D | regSERFLASH.h | 167 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) macro
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| H A D | halSERFLASH.c | 301 {CFG_REG_READ, {0, ISP_SPI_CMD_RDSCUR, NULL, 0, 0, 1}},
4084 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SPI_EnterIBPM()
5682 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register in HAL_SERFLASH_ReadSecureReg()
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