Searched refs:FRC_Miu0Mask (Results 1 – 6 of 6) sorted by relevance
547 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Enable_MiuMask()550 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG0Mask |= MIU_FRC_G0REQUEST_MASK; in MHal_FRC_Enable_MiuMask()551 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG1Mask |= MIU_FRC_G1REQUEST_MASK; in MHal_FRC_Enable_MiuMask()552 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG2Mask |= MIU_FRC_G2REQUEST_MASK; in MHal_FRC_Enable_MiuMask()553 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG3Mask |= MIU_FRC_G3REQUEST_MASK; in MHal_FRC_Enable_MiuMask()554 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG4Mask |= MIU_FRC_G4REQUEST_MASK; in MHal_FRC_Enable_MiuMask()555 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()556 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG6Mask |= MIU_FRC_G6REQUEST_MASK; in MHal_FRC_Enable_MiuMask()566 MHal_FRC_set_miu0mask(pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask); in MHal_FRC_Enable_MiuMask()580 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Disable_MiuMask()[all …]
725 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Enable_MiuMask()728 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG0Mask |= MIU_FRC_G0REQUEST_MASK; in MHal_FRC_Enable_MiuMask()729 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG1Mask |= MIU_FRC_G1REQUEST_MASK; in MHal_FRC_Enable_MiuMask()730 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG2Mask |= MIU_FRC_G2REQUEST_MASK; in MHal_FRC_Enable_MiuMask()731 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG3Mask |= MIU_FRC_G3REQUEST_MASK; in MHal_FRC_Enable_MiuMask()732 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG4Mask |= MIU_FRC_G4REQUEST_MASK; in MHal_FRC_Enable_MiuMask()733 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()734 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG6Mask |= MIU_FRC_G6REQUEST_MASK; in MHal_FRC_Enable_MiuMask()744 MHal_FRC_set_miu0mask(pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask); in MHal_FRC_Enable_MiuMask()758 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Disable_MiuMask()[all …]
708 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Enable_MiuMask()711 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG0Mask |= MIU_FRC_G0REQUEST_MASK; in MHal_FRC_Enable_MiuMask()712 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG1Mask |= MIU_FRC_G1REQUEST_MASK; in MHal_FRC_Enable_MiuMask()713 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG2Mask |= MIU_FRC_G2REQUEST_MASK; in MHal_FRC_Enable_MiuMask()714 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG3Mask |= MIU_FRC_G3REQUEST_MASK; in MHal_FRC_Enable_MiuMask()715 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG4Mask |= MIU_FRC_G4REQUEST_MASK; in MHal_FRC_Enable_MiuMask()716 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()717 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG6Mask |= MIU_FRC_G6REQUEST_MASK; in MHal_FRC_Enable_MiuMask()727 MHal_FRC_set_miu0mask(pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask); in MHal_FRC_Enable_MiuMask()741 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Disable_MiuMask()[all …]
686 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Enable_MiuMask()689 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG0Mask |= MIU_FRC_G0REQUEST_MASK; in MHal_FRC_Enable_MiuMask()690 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG1Mask |= MIU_FRC_G1REQUEST_MASK; in MHal_FRC_Enable_MiuMask()691 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG2Mask |= MIU_FRC_G2REQUEST_MASK; in MHal_FRC_Enable_MiuMask()692 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG3Mask |= MIU_FRC_G3REQUEST_MASK; in MHal_FRC_Enable_MiuMask()693 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG4Mask |= MIU_FRC_G4REQUEST_MASK; in MHal_FRC_Enable_MiuMask()694 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()695 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG6Mask |= MIU_FRC_G6REQUEST_MASK; in MHal_FRC_Enable_MiuMask()705 …MHal_FRC_set_miu2mask(pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask); // FRC not support MIU0, use MI… in MHal_FRC_Enable_MiuMask()719 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask = pXCResourcePrivate->sthal_FRC.FRC_Miu0MaskOld; in MHal_FRC_Disable_MiuMask()[all …]
1298 SC_MIUMASK_t FRC_Miu0Mask; member