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Searched refs:E_SAR_ADC_HSYNC_CH0 (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/projects/tmplib/include/
H A DdrvSAR.h441 E_SAR_ADC_HSYNC_CH0 = 0, /// ADC HSync channel 0 enumerator
/utopia/UTPA2-700.0.x/mxlib/include/
H A DdrvSAR.h438 E_SAR_ADC_HSYNC_CH0 = 0, /// ADC HSync channel 0 enumerator
/utopia/UTPA2-700.0.x/modules/sar/drv/sar/
H A DdrvSAR.c1748 case E_SAR_ADC_HSYNC_CH0: in MDrv_SAR_Adc_SetHSyncCh()
/utopia/UTPA2-700.0.x/projects/build/
H A Dpreprocess.txt53612 E_SAR_ADC_HSYNC_CH0 = 0,