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Searched refs:E_FPLL_FLAG_INITSETDELAY (Results 1 – 5 of 5) sorted by relevance

/utopia/UTPA2-700.0.x/projects/tmplib/include/
H A DapiXC.h1905 E_FPLL_FLAG_INITSETDELAY= 5, ///delay between steps when setting DCLK enumerator
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_display.c3496 if (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_INITSETDELAY] in MDrv_SC_Set_Output_Dclk_Slowly()
3497 && pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETDELAY]) in MDrv_SC_Set_Output_Dclk_Slowly()
3499 u32DelayMs = pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETDELAY]; in MDrv_SC_Set_Output_Dclk_Slowly()
H A Dmdrv_sc_display.c.03494 if (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_INITSETDELAY]
3495 && pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETDELAY])
3497 u32DelayMs = pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETDELAY];
/utopia/UTPA2-700.0.x/mxlib/include/
H A DapiXC.h2160 E_FPLL_FLAG_INITSETDELAY= 5, ///delay between steps when setting DCLK enumerator
/utopia/UTPA2-700.0.x/projects/build/
H A Dpreprocess.txt2126 E_FPLL_FLAG_INITSETDELAY= 5,