Home
last modified time | relevance | path

Searched refs:DRV_DAC_REG (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1C, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1D, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1D, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN_5B_H), 0x01, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TC_CLK_GEN_55_H), 0x01, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1C, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1D, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1D, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN_5B_H), 0x01, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TC_CLK_GEN_55_H), 0x01, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1F, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1D, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1D, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN_5B_H), 0x01, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TC_CLK_GEN_55_H), 0x01, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1F, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1D, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1D, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN_5B_H), 0x01, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TC_CLK_GEN_55_H), 0x01, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1C, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1C, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1C, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN1_28_L), 0x0C, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TABLE_END) , 0x00, 0x00, }
[all …]
H A Dmdrv_dac_tbl.h112 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1C, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1C, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1C, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN1_28_L), 0x0C, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TABLE_END) , 0x00, 0x00, }
[all …]
H A Dmdrv_dac_tbl.h112 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1C, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1C, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1C, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN1_28_L), 0x0C, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TABLE_END) , 0x00, 0x00, }
[all …]
H A Dmdrv_dac_tbl.h112 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c113 { DRV_DAC_REG(REG_TC_CLK_GEN_53_L), 0x1C, 0x10/*ALL*/, },
114 { DRV_DAC_REG(REG_TC_CLK_GEN_53_H), 0x1F, 0x0F/*ALL*/, },
115 { DRV_DAC_REG(REG_TC_CLK_GEN_54_L), 0x01, 0x01/*ALL*/, },
116 { DRV_DAC_REG(REG_TC_CLK_GEN_0A_L), 0x1C, 0x0C/*ALL*/, },
117 { DRV_DAC_REG(REG_TC_CLK_GEN_58_L), 0x0C, 0x0C/*ALL*/, },
118 { DRV_DAC_REG(REG_TC_CLK_GEN_58_H), 0x1C, 0x00/*ALL*/, },
119 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_L), 0x1C, 0x0C/*ALL*/, },
120 { DRV_DAC_REG(REG_TC_CLK_GEN_5A_H), 0x1C, 0x00/*ALL*/, },
121 { DRV_DAC_REG(REG_TC_CLK_GEN1_28_L), 0x0C, 0x00/*ALL*/, },
122 { DRV_DAC_REG(REG_TABLE_END) , 0x00, 0x00, }
[all …]
H A Dmdrv_dac_tbl.h112 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h110 #define DRV_DAC_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) macro