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Searched refs:DIP_W2BYTEMSK (Results 1 – 6 of 6) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c254 #define DIP_W2BYTEMSK(u32Id,u32Reg,u16Val,u16Mask)\ macro
674 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
678 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
682 DIP_W2BYTEMSK(0, REG_SC_BK3C_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
695 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
697 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
702 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
704 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
709 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
711 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
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/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c255 #define DIP_W2BYTEMSK(u32Id,u32Reg,u16Val,u16Mask)\ macro
675 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
679 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
683 DIP_W2BYTEMSK(0, REG_SC_BK3C_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
696 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
698 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
703 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
705 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
710 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
712 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c255 #define DIP_W2BYTEMSK(u32Id,u32Reg,u16Val,u16Mask)\ macro
675 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
679 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
683 DIP_W2BYTEMSK(0, REG_SC_BK3C_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
696 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
698 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
703 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
705 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
710 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
712 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c255 #define DIP_W2BYTEMSK(u32Id,u32Reg,u16Val,u16Mask)\ macro
675 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
679 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
683 DIP_W2BYTEMSK(0, REG_SC_BK3C_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
696 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
698 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
703 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
705 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
710 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, BIT(1), BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
712 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, 0x00 , BIT(1)); in Hal_SC_DWIN_set_pre_align_pixel()
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/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_dip.c333 #define DIP_W2BYTEMSK(u32Id,u32Reg,u16Val,u16Mask)\ macro
919 DIP_W2BYTEMSK(0, REG_SC_BK43_7F_L,(u16temp-1),BMASK(6:0)); in HAL_XC_DIP_DI_Read_FIFO()
921 DIP_W2BYTEMSK(0, REG_SC_BK44_7F_L,(u16temp-1),BMASK(6:0)); in HAL_XC_DIP_DI_Read_FIFO()
951 DIP_W2BYTEMSK(0, REG_SC_BK36_6F_L,DIPW_TILE_LINEAR_REQUEST_MAX,BMASK(6:0)); in HAL_XC_DIP_Write_ReqNum()
956 DIP_W2BYTEMSK(0, REG_SC_BK36_6F_L,(u16MiuCnt/2),BMASK(5:0)); in HAL_XC_DIP_Write_ReqNum()
958 DIP_W2BYTEMSK(0, REG_SC_BK36_6F_L,((u16MiuCnt/2)-1),BMASK(5:0)); in HAL_XC_DIP_Write_ReqNum()
967 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L,DIPW_TILE_REQUEST_MAX,BMASK(6:0)); in HAL_XC_DIP_Write_ReqNum()
977 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L,((u16temp-1)&0xFFFE),BMASK(6:0)); in HAL_XC_DIP_Write_ReqNum()
993 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
997 DIP_W2BYTEMSK(0, REG_SC_BK3B_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
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/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_dip.c342 #define DIP_W2BYTEMSK(u32Id,u32Reg,u16Val,u16Mask)\ macro
965 DIP_W2BYTEMSK(0, REG_SC_BK43_7F_L,(u16temp-1),BMASK(6:0)); in HAL_XC_DIP_DI_Read_FIFO()
967 DIP_W2BYTEMSK(0, REG_SC_BK44_7F_L,(u16temp-1),BMASK(6:0)); in HAL_XC_DIP_DI_Read_FIFO()
997 DIP_W2BYTEMSK(0, REG_SC_BK36_6F_L,DIPW_TILE_LINEAR_REQUEST_MAX,BMASK(6:0)); in HAL_XC_DIP_Write_ReqNum()
1002 DIP_W2BYTEMSK(0, REG_SC_BK36_6F_L,(u16MiuCnt/2),BMASK(5:0)); in HAL_XC_DIP_Write_ReqNum()
1004 DIP_W2BYTEMSK(0, REG_SC_BK36_6F_L,((u16MiuCnt/2)-1),BMASK(5:0)); in HAL_XC_DIP_Write_ReqNum()
1013 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L,DIPW_TILE_REQUEST_MAX,BMASK(6:0)); in HAL_XC_DIP_Write_ReqNum()
1023 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L,((u16temp-1)&0xFFFE),BMASK(6:0)); in HAL_XC_DIP_Write_ReqNum()
1039 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1043 DIP_W2BYTEMSK(0, REG_SC_BK3B_30_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
[all …]