Searched refs:CLK_STC_PVR2_DISABLE (Results 1 – 5 of 5) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | halTSP.c | 4134 #define CLK_STC_PVR2_DISABLE 0x0001UL macro
4182 u32RegClkMask = CLK_STC_PVR2_MASK|CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4456 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_I… in HAL_TSP_PowerCtrl()
4507 … SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)), CLK_STC_PVR2_DISABLE)); in HAL_TSP_PowerCtrl()
4608 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_I… in HAL_TSP_PowerCtrl()
4657 … SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2)), CLK_STC_PVR2_DISABLE)); in HAL_TSP_PowerCtrl()
4732 #undef CLK_STC_PVR2_DISABLE
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | halTSP.c | 4385 #define CLK_STC_PVR2_DISABLE 0x0001UL macro
4453 u32RegClkMask = CLK_STC_PVR2_MASK|CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4727 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4787 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4907 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4960 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
5055 #undef CLK_STC_PVR2_DISABLE
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | halTSP.c | 4368 #define CLK_STC_PVR2_DISABLE 0x0001UL macro
4436 u32RegClkMask = CLK_STC_PVR2_MASK|CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4710 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4770 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4890 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4943 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
5038 #undef CLK_STC_PVR2_DISABLE
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | halTSP.c | 4459 #define CLK_STC_PVR2_DISABLE 0x0001UL macro
4525 u32RegClkMask = CLK_STC_PVR2_MASK|CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4793 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4853 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4967 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
5019 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
5111 #undef CLK_STC_PVR2_DISABLE
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | halTSP.c | 4420 #define CLK_STC_PVR2_DISABLE 0x0001UL macro
4486 u32RegClkMask = CLK_STC_PVR2_MASK|CLK_STC_PVR2_DISABLE|CLK_STC_PVR2_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4754 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4814 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4928 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_PVR2_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4980 …(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
5072 #undef CLK_STC_PVR2_DISABLE
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