Searched refs:CLK_STC_PVR1_DISABLE (Results 1 – 5 of 5) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | halTSP.c | 4127 #define CLK_STC_PVR1_DISABLE 0x0100UL macro
4176 u32RegClkMask = CLK_STC_PVR1_MASK|CLK_STC_PVR1_DISABLE|CLK_STC_PVR1_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4452 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4503 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
4604 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4653 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
4726 #undef CLK_STC_PVR1_DISABLE
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | halTSP.c | 4378 #define CLK_STC_PVR1_DISABLE 0x0100UL macro
4447 u32RegClkMask = CLK_STC_PVR1_MASK|CLK_STC_PVR1_DISABLE|CLK_STC_PVR1_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4723 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4783 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
4903 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4956 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
5050 #undef CLK_STC_PVR1_DISABLE
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | halTSP.c | 4361 #define CLK_STC_PVR1_DISABLE 0x0100UL macro
4430 u32RegClkMask = CLK_STC_PVR1_MASK|CLK_STC_PVR1_DISABLE|CLK_STC_PVR1_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4706 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4766 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
4886 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4939 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
5033 #undef CLK_STC_PVR1_DISABLE
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | halTSP.c | 4453 #define CLK_STC_PVR1_DISABLE 0x0100UL macro
4519 u32RegClkMask = CLK_STC_PVR1_MASK|CLK_STC_PVR1_DISABLE|CLK_STC_PVR1_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4789 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4849 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
4963 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
5015 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
5106 #undef CLK_STC_PVR1_DISABLE
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | halTSP.c | 4414 #define CLK_STC_PVR1_DISABLE 0x0100UL macro
4480 u32RegClkMask = CLK_STC_PVR1_MASK|CLK_STC_PVR1_DISABLE|CLK_STC_PVR1_INVERT; in HAL_TSP_SetPVRTimeStampClk()
4750 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4810 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
4924 …_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)) & ~(CLK_STC_PVR1_DISABLE|CLK_STC_PVR… in HAL_TSP_PowerCtrl()
4976 …2L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_MM1_PVR1)), (CLK_STC_MM1_DISABLE|CLK_STC_PVR1_DISABLE))); in HAL_TSP_PowerCtrl()
5067 #undef CLK_STC_PVR1_DISABLE
|