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Searched refs:CLK_STC_FIQ0_DISABLE (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c4390 #define CLK_STC_FIQ0_DISABLE 0x0100UL macro
4729 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4787 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
4909 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4960 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
5059 #undef CLK_STC_FIQ0_DISABLE
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c4373 #define CLK_STC_FIQ0_DISABLE 0x0100UL macro
4712 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4770 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
4892 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4943 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
5042 #undef CLK_STC_FIQ0_DISABLE
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c4464 #define CLK_STC_FIQ0_DISABLE 0x0100UL macro
4795 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4853 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
4969 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
5019 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
5115 #undef CLK_STC_FIQ0_DISABLE
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c4425 #define CLK_STC_FIQ0_DISABLE 0x0100UL macro
4756 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4814 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
4930 …HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)) & ~(CLK_STC_FIQ0_DISABLE|CLK_STC_FIQ… in HAL_TSP_PowerCtrl()
4980 …_R((REG32_L *)(_virtRegBase+CKG_TSP_STC_PVR2_FIQ0)), (CLK_STC_PVR2_DISABLE|CLK_STC_FIQ0_DISABLE))); in HAL_TSP_PowerCtrl()
5076 #undef CLK_STC_FIQ0_DISABLE