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Searched refs:CLK0_CKG_SPI_MASK (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/flash/hal/mooney/flash/serial/
H A DhalSERFLASH.c1810 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1814 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1818 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1822 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1826 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h310 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/M7621/flash/serial/
H A DhalSERFLASH.c1847 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1851 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1855 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1859 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1863 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h310 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/mainz/flash/serial/
H A DhalSERFLASH.c1818 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1822 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1826 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1830 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1834 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h311 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/maserati/flash/serial/
H A DhalSERFLASH.c1847 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1851 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1855 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1859 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1863 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h310 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/M7821/flash/serial/
H A DhalSERFLASH.c1847 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1851 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1855 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1859 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1863 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h310 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/messi/flash/serial/
H A DhalSERFLASH.c1818 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1822 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1826 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1830 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1834 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h311 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/maxim/flash/serial/
H A DhalSERFLASH.c1847 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1851 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1855 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1859 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1863 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h310 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/macan/flash/serial/
H A DhalSERFLASH.c1810 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1814 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1818 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1822 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1826 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h310 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/manhattan/flash/serial/
H A DhalSERFLASH.c1848 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1852 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1856 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1860 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1864 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h310 #define CLK0_CKG_SPI_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/maldives/flash/serial/
H A DhalSERFLASH.c1944 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1948 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1952 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1956 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1960 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
H A DregSERFLASH.h313 #define CLK0_CKG_SPI_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/mustang/flash/serial/
H A DhalSERFLASH.c1966 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1970 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1974 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1978 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
1982 CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi in HAL_SERFLASH_SetCKG()
/utopia/UTPA2-700.0.x/modules/flash/hal/k6lite/flash/serial/
H A DregSERFLASH.h335 #define CLK0_CKG_SPI_MASK BMASK(4:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/kano/flash/serial/
H A DregSERFLASH.h335 #define CLK0_CKG_SPI_MASK BMASK(4:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/curry/flash/serial/
H A DregSERFLASH.h335 #define CLK0_CKG_SPI_MASK BMASK(4:2) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/k6/flash/serial/
H A DregSERFLASH.h335 #define CLK0_CKG_SPI_MASK BMASK(4:2) macro

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