Home
last modified time | relevance | path

Searched refs:BK_AFEC_DC (Results 1 – 25 of 26) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c3821 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
3838 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
3856 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c7183 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7200 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7218 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c7309 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c7309 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c7256 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7273 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7291 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c7309 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c7183 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7200 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7218 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c3821 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
3838 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
3856 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c7309 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c7309 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c3820 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
3837 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
3855 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c7199 u8Ctl = RIU_ReadByte( BK_AFEC_DC ); in HAL_AVD_AFEC_SetRegFromDSP()
7216 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7234 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
H A DregAVD.h369 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/
H A Dve_Analog_Reg.h705 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) macro

12