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Searched refs:BK_AFEC_67 (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7386 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7512 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7512 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7402 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c4024 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7459 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7512 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7512 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c4024 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7386 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c7512 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DregAVD.h252 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro
H A DhalAVD.c4023 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/
H A Dve_Analog_Reg.h588 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) macro

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