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Searched refs:BK_AFEC_55 (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c3939 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
4085 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4087 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4106 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4108 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4127 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4129 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4727 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
4729 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c7301 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7447 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7449 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7468 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7470 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7489 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7491 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8089 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8091 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c7427 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7573 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7575 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7594 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7596 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7615 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7617 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8245 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8247 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c7427 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7573 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7575 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7594 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7596 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7615 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7617 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8245 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8247 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c7374 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7520 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7522 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7541 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7543 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7562 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7564 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8183 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8185 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c7427 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7573 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7575 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7594 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7596 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7615 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7617 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8246 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8248 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c7301 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7447 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7449 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7468 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7470 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7489 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7491 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8089 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8091 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c3939 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
4085 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4087 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4106 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4108 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4127 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4129 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4727 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
4729 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c7427 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7573 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7575 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7594 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7596 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7615 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7617 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8245 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8247 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c7427 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7573 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7575 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7594 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7596 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7615 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7617 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8246 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8248 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c3938 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
4084 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4086 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4105 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4107 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4126 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4128 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4726 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
4728 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c7317 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7463 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7465 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7484 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7486 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7505 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7507 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
8126 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8128 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
H A DregAVD.h234 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) macro
/utopia/UTPA2-700.0.x/modules/vd/drv/avd/
H A DAVD.c2943 u8tmp = HAL_AVD_GetReg(BK_AFEC_55); in Drv_AVD_SetFactoryPara()
2944 HAL_AVD_SetReg(BK_AFEC_55,u8tmp|BIT(2)); in Drv_AVD_SetFactoryPara()
2946 HAL_AVD_SetReg(BK_AFEC_55,u8tmp &(~BIT(2))); in Drv_AVD_SetFactoryPara()

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