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Searched refs:BK_AFEC_43 (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7446 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7572 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7572 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c4084 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7519 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7572 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7572 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c4084 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7446 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c7572 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DregAVD.h216 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro
H A DhalAVD.c4083 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
/utopia/UTPA2-700.0.x/modules/vd/drv/avd/
H A DAVD.c2940 u8tmp = HAL_AVD_GetReg(BK_AFEC_43); in Drv_AVD_SetFactoryPara()
2942 HAL_AVD_SetReg(BK_AFEC_43,u8tmp |(u8Value & (BIT(5)|BIT(6)))); in Drv_AVD_SetFactoryPara()
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/
H A Dve_Analog_Reg.h552 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) macro

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