Searched refs:wr (Results 1 – 2 of 2) sorted by relevance
38 #define FIFO_WRITE(size, count, wr, rd) \ argument40 wr++; \41 if (wr >= size) wr = 0; \46 #define FIFO_READ(size, count, wr, rd) \ argument
423 - [hal_av1d_vdpu383]: modify av1 segid wr/rd base config