Searched refs:reg50_dec_ctrl (Results 1 – 8 of 8) sorted by relevance
168 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0; in hal_vp8_init_hwcfg()169 reg->reg50_dec_ctrl.sw_dec_scmd_dis = 0; in hal_vp8_init_hwcfg()170 reg->reg50_dec_ctrl.sw_dec_adv_pre_dis = 0; in hal_vp8_init_hwcfg()171 reg->reg50_dec_ctrl.sw_dec_latency = 0; in hal_vp8_init_hwcfg()519 regs->reg50_dec_ctrl.sw_skip_mode = !pic_param->mb_no_coeff_skip; in hal_vp8d_vdpu2_gen_regs()539 regs->reg50_dec_ctrl.sw_filtering_dis = 1; in hal_vp8d_vdpu2_gen_regs()
47 } reg50_dec_ctrl; member
41 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0; in jpegd_regs_init()42 reg->reg50_dec_ctrl.sw_dec_scmd_dis = DEC_SCMD_DISABLE; in jpegd_regs_init()43 reg->reg50_dec_ctrl.sw_dec_latency = DEC_LATENCY_COMPENSATION; in jpegd_regs_init()641 reg->reg50_dec_ctrl.sw_filtering_dis = 1; in jpegd_gen_regs()
226 } reg50_dec_ctrl; member
67 regs->reg50_dec_ctrl.sw_filtering_dis = 1; in vpu2_h263d_setup_regs_by_syntax()
37 } reg50_dec_ctrl; member
102 regs->reg50_dec_ctrl.sw_dblk_flt_dis = 1; in vdpu2_mpg4d_setup_regs_by_syntax()