Home
last modified time | relevance | path

Searched refs:index (Results 1 – 25 of 94) sorted by relevance

1234

/rockchip-linux_mpp/mpp/codec/dec/h263/
H A Dh263d_parser.c269 RK_S32 index = hdr_curr->slot_idx; in mpp_h263_parser_flush() local
273 if (!hdr_curr->enqueued && index >= 0) { in mpp_h263_parser_flush()
274 mpp_buf_slot_set_flag(slots, index, SLOT_QUEUE_USE); in mpp_h263_parser_flush()
275 mpp_buf_slot_enqueue(slots, index, QUEUE_DISPLAY); in mpp_h263_parser_flush()
290 RK_S32 index = hdr_curr->slot_idx; in mpp_h263_parser_reset() local
294 if (index >= 0) { in mpp_h263_parser_reset()
295 mpp_buf_slot_clr_flag(slots, index, SLOT_CODEC_USE); in mpp_h263_parser_reset()
299 index = hdr_ref0->slot_idx; in mpp_h263_parser_reset()
300 if (index >= 0) { in mpp_h263_parser_reset()
301 mpp_buf_slot_clr_flag(slots, index, SLOT_CODEC_USE); in mpp_h263_parser_reset()
[all …]
/rockchip-linux_mpp/mpp/base/inc/
H A Dmpp_buf_slot.h177 MPP_RET mpp_buf_slot_get_unused(MppBufSlots slots, RK_S32 *index);
207 MPP_RET mpp_buf_slot_set_flag(MppBufSlots slots, RK_S32 index, SlotUsageType type);
208 MPP_RET mpp_buf_slot_clr_flag(MppBufSlots slots, RK_S32 index, SlotUsageType type);
219 MPP_RET mpp_buf_slot_enqueue(MppBufSlots slots, RK_S32 index, SlotQueueType type);
220 MPP_RET mpp_buf_slot_dequeue(MppBufSlots slots, RK_S32 *index, SlotQueueType type);
230 MPP_RET mpp_buf_slot_set_prop(MppBufSlots slots, RK_S32 index, SlotPropType type, void *val);
231 MPP_RET mpp_buf_slot_get_prop(MppBufSlots slots, RK_S32 index, SlotPropType type, void *val);
262 MPP_RET mpp_buf_slot_reset(MppBufSlots slots, RK_S32 index); //rest slot status when info_change no…
265 MPP_RET mpp_buf_slot_default_info(MppBufSlots slots, RK_S32 index, void *val);
/rockchip-linux_mpp/mpp/base/
H A Dmpp_bitput.c24 bp->index = 0; in mpp_set_bitput_ctx()
39 if (bp->index >= bp->buflen) return; in mpp_put_bits()
45 bp->pbuf[bp->index] = bp->bvalue; in mpp_put_bits()
47 bp->index++; in mpp_put_bits()
50 if (bp->index >= bp->buflen) in mpp_put_bits()
53 bp->pbuf[bp->index] = bp->bvalue; in mpp_put_bits()
62 word_offset = (align_bits >= 64) ? ((bp->index & (((align_bits & 0xfe0) >> 6) - 1)) << 6) : 0; in mpp_put_align()
H A Dmpp_buf_slot.c166 RK_S32 index; member
185 RK_S32 index; member
537 static void buf_slot_logs_write(MppBufSlotLogs *logs, RK_S32 index, MppBufSlotOps op, in buf_slot_logs_write() argument
543 log->index = index; in buf_slot_logs_write()
567 log->index, op_string[log->ops], log->status_in.val, log->status_out.val); in buf_slot_logs_dump()
607 RK_S32 index = slot->index; in slot_ops_with_log() local
645 mpp_err("can not clr hal_input on slot %d\n", slot->index); in slot_ops_with_log()
657 mpp_err("can not clr hal_output on slot %d\n", slot->index); in slot_ops_with_log()
678 mpp_err("can not clr queue_use on slot %d\n", slot->index); in slot_ops_with_log()
708 impl->slots_idx, index, op_string[op], arg, before.val, status.val); in slot_ops_with_log()
[all …]
H A Dmpp_meta.c273 return info ? info->index : -1; in MPP_SINGLETON()
587 impl->vals[node->index].val_s32); in mpp_meta_dump()
591 impl->vals[node->index].val_s64); in mpp_meta_dump()
597 impl->vals[node->index].val_ptr); in mpp_meta_dump()
615 RK_S32 index; \
620 index = get_index_of_key_f(key, key_type); \
621 if (index < 0) \
623 meta_val = &impl->vals[index]; \
626 if (index == user_data_index) { \
628 } else if (index == user_datas_index) { \
[all …]
/rockchip-linux_mpp/utils/
H A Dmpp_enc_roi_utils.c357 RK_U32 index = pos / 32; in set_roi_pos_val() local
360 buf[index] = buf[index] | (value << bits); in set_roi_pos_val()
364 #define set_roi_qpadj(buf, index, val) \ argument
366 RK_U32 offset = 425 + index; \
370 #define set_roi_force_split(buf, index, val) \ argument
372 RK_U32 offset = 340 + index; \
376 #define set_roi_force_intra(buf, index, val) \ argument
378 RK_U32 offset = 170 + index * 2; \
382 #define set_roi_force_inter(buf, index, val) \ argument
384 RK_U32 offset = index * 2; \
[all …]
H A Dcamera_source.c137 input.index = 0; in camera_source_init()
140 ++input.index; in camera_source_init()
173 fmtdesc.index = 0; in camera_source_init()
180 fmtdesc.index++; in camera_source_init()
228 buf.index = i; in camera_source_init()
268 expbuf.index = i; in camera_source_init()
280 info.index = (buf_len & 0xf8000000) >> 27; in camera_source_init()
292 buf.index = i; in camera_source_init()
349 buf.index = i; in camera_source_deinit()
351 if (ctx->fbuf[buf.index].buffer) { in camera_source_deinit()
[all …]
H A Dmpi_dec_utils.h97 RK_S32 index; member
151 MPP_RET reader_index_read(FileReader reader, RK_S32 index, FileBufSlot **buf);
/rockchip-linux_mpp/test/
H A Dmpi_rc.cfg2 # index type can be 'frm' or 'msec', frm stand for event trigger at frame index,
4 index: frm
6 # index is 1, the last index is 171, and loop is 200, when the last event occur,
/rockchip-linux_mpp/osal/
H A Dmpp_mem.c96 rk_s32 index; member
103 rk_u32 index; member
194 if (node->index < 0) in mpp_mem_srv_dump()
198 node->index, node->caller, node->size, node->ptr); in mpp_mem_srv_dump()
206 if (node->index < 0) in mpp_mem_srv_dump()
210 node->index, node->caller, node->size, node->ptr); in mpp_mem_srv_dump()
226 log->index, ops2str[log->ops], log->caller, in mpp_mem_srv_dump()
320 if (node->index >= 0 && node->ptr == ptr) { in reset_node()
344 log->index = srv->log_index++; in add_log()
381 if (node->index < 0) { in add_node()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_com.c42 void vpu_mpg4d_get_buffer_by_index(hal_mpg4_ctx *ctx, RK_S32 index, MppBuffer *buffer) in vpu_mpg4d_get_buffer_by_index() argument
44 if (index >= 0) { in vpu_mpg4d_get_buffer_by_index()
45 mpp_buf_slot_get_prop(ctx->frm_slots, index, SLOT_BUFFER, buffer); in vpu_mpg4d_get_buffer_by_index()
/rockchip-linux_mpp/mpp/codec/enc/h265/
H A Dh265e_dpb.c308 RK_U32 index = 0; in h265e_dpb_apply_rps() local
313 for (index = 0; index < MPP_ARRAY_ELEMS(dpb->frame_list); index++) { in h265e_dpb_apply_rps()
314 outPic = &frame_list[index]; in h265e_dpb_apply_rps()
347 RK_U32 index = 0; in h265e_dpb_dec_refresh_marking() local
358 for (index = 0; index < MPP_ARRAY_ELEMS(dpb->frame_list); index++) { in h265e_dpb_dec_refresh_marking()
359 H265eDpbFrm *frame = &frame_List[index]; in h265e_dpb_dec_refresh_marking()
379 for (index = 0; index < MPP_ARRAY_ELEMS(dpb->frame_list); index++) { in h265e_dpb_dec_refresh_marking()
381 H265eDpbFrm *frame = &frame_list[index]; in h265e_dpb_dec_refresh_marking()
752 RK_U32 index = 0, i = 0; in h265e_dpb_proc_cpb() local
761 for (index = 0; index < MPP_ARRAY_ELEMS(dpb->frame_list); index++) { in h265e_dpb_proc_cpb()
[all …]
H A Dh265e_ps.c462 RK_S32 index; in h265e_set_pps() local
488 for (index = 0; index < pps->m_nNumTileColumnsMinus1; index++) { in h265e_set_pps()
489 tile_width = (index + 1) * mb_w / (pps->m_nNumTileColumnsMinus1 + 1) - in h265e_set_pps()
490 index * mb_w / (pps->m_nNumTileColumnsMinus1 + 1); in h265e_set_pps()
491 pps->m_nTileColumnWidthArray[index] = tile_width; in h265e_set_pps()
492 pps->m_nTileRowHeightArray[index] = mb_h; in h265e_set_pps()
494 tile_width = mb_w - index * mb_w / (pps->m_nNumTileColumnsMinus1 + 1); in h265e_set_pps()
495 pps->m_nTileColumnWidthArray[index] = tile_width; in h265e_set_pps()
496 pps->m_nTileRowHeightArray[index] = mb_h; in h265e_set_pps()
/rockchip-linux_mpp/mpp/codec/dec/mpg4/
H A Dmpg4d_parser.c1126 RK_S32 index = hdr_ref0->slot_idx; in mpp_mpg4_parser_flush() local
1130 if (!hdr_ref0->enqueued && index >= 0) { in mpp_mpg4_parser_flush()
1131 mpp_buf_slot_set_flag(slots, index, SLOT_QUEUE_USE); in mpp_mpg4_parser_flush()
1132 mpp_buf_slot_enqueue(slots, index, QUEUE_DISPLAY); in mpp_mpg4_parser_flush()
1147 RK_S32 index = hdr_ref0->slot_idx; in mpp_mpg4_parser_reset() local
1151 if (index >= 0) { in mpp_mpg4_parser_reset()
1153 mpp_buf_slot_set_flag(slots, index, SLOT_QUEUE_USE); in mpp_mpg4_parser_reset()
1154 mpp_buf_slot_enqueue(slots, index, QUEUE_DISPLAY); in mpp_mpg4_parser_reset()
1157 mpp_buf_slot_clr_flag(slots, index, SLOT_CODEC_USE); in mpp_mpg4_parser_reset()
1161 index = hdr_ref1->slot_idx; in mpp_mpg4_parser_reset()
[all …]
/rockchip-linux_mpp/mpp/codec/dec/jpeg/
H A Djpegd_parser.c321 int index, i; in jpegd_decode_dqt() local
340 READ_BITS(gb, 4, &index); in jpegd_decode_dqt()
341 if (index >= QUANTIZE_TABLE_ID_BUTT) { in jpegd_decode_dqt()
345 jpegd_dbg_marker("quantize tables ID=%d\n", index); in jpegd_decode_dqt()
350 syntax->quant_matrixes[index][i] = value; in jpegd_decode_dqt()
358 mpp_log("******Start to print quantize table %d******\n", index); in jpegd_decode_dqt()
363 syntax->quant_matrixes[index][i + 0], in jpegd_decode_dqt()
364 syntax->quant_matrixes[index][i + 1], in jpegd_decode_dqt()
365 syntax->quant_matrixes[index][i + 2], in jpegd_decode_dqt()
366 syntax->quant_matrixes[index][i + 3], in jpegd_decode_dqt()
[all …]
/rockchip-linux_mpp/mpp/codec/
H A Dmpp_dec_no_thread.c327 RK_S32 index = task_dec->refer[i]; in mpp_dec_decode() local
328 if (index >= 0) in mpp_dec_decode()
329 mpp_buf_slot_clr_flag(frame_slots, index, SLOT_HAL_INPUT); in mpp_dec_decode()
354 RK_S32 index; in mpp_dec_reset_no_thread() local
380 index = task_dec->refer[i]; in mpp_dec_reset_no_thread()
381 if (index >= 0) in mpp_dec_reset_no_thread()
382 mpp_buf_slot_clr_flag(frame_slots, index, SLOT_HAL_INPUT); in mpp_dec_reset_no_thread()
387 while (MPP_OK == mpp_buf_slot_dequeue(frame_slots, &index, QUEUE_DISPLAY)) { in mpp_dec_reset_no_thread()
391 mpp_buf_slot_get_prop(frame_slots, index, SLOT_BUFFER, &buffer); in mpp_dec_reset_no_thread()
394 mpp_buf_slot_clr_flag(frame_slots, index, SLOT_QUEUE_USE); in mpp_dec_reset_no_thread()
H A Dmpp_dec.c194 void mpp_dec_put_frame(Mpp *mpp, RK_S32 index, HalDecTaskFlag flags) in mpp_dec_put_frame() argument
205 if (index >= 0) { in mpp_dec_put_frame()
208 mpp_buf_slot_get_prop(slots, index, SLOT_FRAME_PTR, &frame); in mpp_dec_put_frame()
264 vproc_task->input = index; in mpp_dec_put_frame()
274 index = 0; in mpp_dec_put_frame()
280 mpp_assert(index >= 0); in mpp_dec_put_frame()
334 mpp_buf_slot_get_prop(slots, index, SLOT_BUFFER, &buffer); in mpp_dec_put_frame()
348 vproc_task->input = index; in mpp_dec_put_frame()
351 mpp_buf_slot_set_flag(slots, index, SLOT_QUEUE_USE); in mpp_dec_put_frame()
352 mpp_buf_slot_enqueue(slots, index, QUEUE_DEINTERLACE); in mpp_dec_put_frame()
[all …]
H A Dmpp_dec_normal.c158 RK_S32 index; in reset_parser_thread() local
178 index = task_dec->refer[i]; in reset_parser_thread()
179 if (index >= 0) in reset_parser_thread()
180 mpp_buf_slot_clr_flag(frame_slots, index, SLOT_HAL_INPUT); in reset_parser_thread()
187 while (MPP_OK == mpp_buf_slot_dequeue(frame_slots, &index, QUEUE_DISPLAY)) { in reset_parser_thread()
190 mpp_buf_slot_get_prop(frame_slots, index, SLOT_BUFFER, &buffer); in reset_parser_thread()
193 mpp_buf_slot_clr_flag(frame_slots, index, SLOT_QUEUE_USE); in reset_parser_thread()
250 RK_S32 index = -1; in reset_hal_thread() local
258 while (MPP_OK == mpp_buf_slot_dequeue(frame_slots, &index, QUEUE_DISPLAY)) { in reset_hal_thread()
259 mpp_dec_put_frame(mpp, index, flag); in reset_hal_thread()
[all …]
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu5xx_common.h30 #define SET_OSD_INV_THR(index, reg, region)\ argument
31 if(region[index].inverse) \
32 reg.osd_ithd_r##index = ENC_DEFAULT_OSD_INV_THR;
/rockchip-linux_mpp/mpp/hal/
H A Dhal_task.c24 RK_S32 index; member
86 task->index = i; in hal_task_group_init()
179 mpp_assert(impl->index < group->task_count); in hal_task_hnd_set_status()
202 mpp_assert(impl->index < group->task_count); in hal_task_hnd_set_info()
221 mpp_assert(impl->index < group->task_count); in hal_task_hnd_get_info()
240 mpp_assert(impl->index < group->task_count); in hal_task_hnd_get_data()
/rockchip-linux_mpp/osal/driver/
H A Dmpp_device.c190 MPP_RET mpp_dev_set_reg_offset(MppDev dev, RK_S32 index, RK_U32 offset) in mpp_dev_set_reg_offset() argument
194 trans_cfg.reg_idx = index; in mpp_dev_set_reg_offset()
237 MPP_RET mpp_dev_multi_offset_update(MppDevRegOffCfgs *cfgs, RK_S32 index, RK_U32 offset) in mpp_dev_multi_offset_update() argument
256 if (cfg->reg_idx == (RK_U32)index) { in mpp_dev_multi_offset_update()
262 cfg->reg_idx = index; in mpp_dev_multi_offset_update()
/rockchip-linux_mpp/mpp/codec/dec/dummy/
H A Ddummy_dec_api.c248 RK_S32 index = p->slot_index[i]; in dummy_dec_parse() local
249 if (index >= 0) { in dummy_dec_parse()
250 task->refer[i] = index; in dummy_dec_parse()
251 mpp_buf_slot_set_flag(slots, index, SLOT_HAL_INPUT); in dummy_dec_parse()
252 mpp_buf_slot_set_flag(slots, index, SLOT_CODEC_USE); in dummy_dec_parse()
/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_api.c30 void vpu_h263d_get_buffer_by_index(hal_h263_ctx *ctx, RK_S32 index, in vpu_h263d_get_buffer_by_index() argument
33 if (index >= 0) { in vpu_h263d_get_buffer_by_index()
34 mpp_buf_slot_get_prop(ctx->frm_slots, index, SLOT_BUFFER, buffer); in vpu_h263d_get_buffer_by_index()
/rockchip-linux_mpp/mpp/hal/rkdec/
H A Dvdpu34x_com.c161 RK_U32 index = 0; in vdpu34x_set_rcbinfo() local
164 index = rcb_priority[i]; in vdpu34x_set_rcbinfo()
171 if (index == RCB_INTER_ROW) in vdpu34x_set_rcbinfo()
174 rcb_cfg.reg_idx = info[index].reg; in vdpu34x_set_rcbinfo()
175 rcb_cfg.size = info[index].size; in vdpu34x_set_rcbinfo()
/rockchip-linux_mpp/inc/
H A Dmpp_buffer.h180 int index; member
252 #define mpp_buffer_set_index(buffer, index) \ argument
253 mpp_buffer_set_index_with_caller(buffer, index, __FUNCTION__)
316 MPP_RET mpp_buffer_set_index_with_caller(MppBuffer buffer, int index, const char *caller);

1234