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/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu2_reg_tbl.h22 #define BIT(n) (1<<(n)) macro
103 #define VEPU_REG_AXI_CTRL_BIRST_DISABLE BIT(0)
113 #define VEPU_REG_DISABLE_QUARTER_PIXEL_MV BIT(28)
116 #define VEPU_REG_ENTROPY_CODING_MODE BIT(20)
117 #define VEPU_REG_H264_TRANS8X8_MODE BIT(17)
118 #define VEPU_REG_H264_INTER4X4_MODE BIT(16)
119 #define VEPU_REG_H264_STREAM_MODE BIT(15)
171 #define VEPU_REG_VP8_SEGMENT_MAP_UPDATE BIT(30)
172 #define VEPU_REG_VP8_SEGMENT_EN BIT(29)
173 #define VEPU_REG_VP8_MV_REF_IDX2_EN BIT(28)
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H A Dhal_h264e_vepu1_reg_tbl.h22 #define BIT(n) (1<<(n)) macro
26 #define VEPU_REG_INTERRUPT_SLICE_READY BIT(8)
27 #define VEPU_REG_INTERRUPT_TIMEOUT BIT(6)
28 #define VEPU_REG_INTERRUPT_BUFFER_FULL BIT(5)
29 #define VEPU_REG_INTERRUPT_RESET BIT(4)
30 #define VEPU_REG_INTERRUPT_BUS_ERROR BIT(3)
31 #define VEPU_REG_INTERRUPT_FRAME_READY BIT(2)
32 #define VEPU_REG_INTERRUPT_DIS_BIT BIT(1)
33 #define VEPU_REG_INTERRUPT_BIT BIT(0)
38 #define VEPU_REG_OUTPUT_SWAP16 BIT(15)
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