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Searched refs:write_aux_reg (Results 1 – 3 of 3) sorted by relevance

/rk3399_rockchip-uboot/arch/arc/lib/
H A Dcache.c55 write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); in __before_slc_op()
76 write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH); in __after_slc_op()
95 write_aux_reg(aux_cmd, paddr); in __slc_line_loop()
110 write_aux_reg(aux, 0x1); in __slc_entire_op()
234 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, in cache_init()
242 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); in cache_init()
243 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); in cache_init()
244 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); in cache_init()
264 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & in icache_enable()
271 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | in icache_disable()
[all …]
/rk3399_rockchip-uboot/drivers/timer/
H A Darc_timer.c76 write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); in arc_timer_probe()
78 write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); in arc_timer_probe()
80 write_aux_reg(ARC_AUX_TIMER0_CNT, 0); in arc_timer_probe()
84 write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE); in arc_timer_probe()
86 write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff); in arc_timer_probe()
88 write_aux_reg(ARC_AUX_TIMER1_CNT, 0); in arc_timer_probe()
/rk3399_rockchip-uboot/arch/arc/include/asm/
H A Darcregs.h73 #define write_aux_reg(reg_immed, val) \ macro