1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip UFS Host Controller driver 4 * 5 * Copyright (C) 2024 Rockchip Electronics Co.Ltd. 6 */ 7 8 #ifndef _UFS_ROCKCHIP_H_ 9 #define _UFS_ROCKCHIP_H_ 10 11 #define UFS_MAX_CLKS 3 12 13 #define SEL_TX_LANE0 0x0 14 #define SEL_TX_LANE1 0x1 15 #define SEL_TX_LANE2 0x2 16 #define SEL_TX_LANE3 0x3 17 #define SEL_RX_LANE0 0x4 18 #define SEL_RX_LANE1 0x5 19 #define SEL_RX_LANE2 0x6 20 #define SEL_RX_LANE3 0x7 21 22 #define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022 23 #define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023 24 25 /* Vendor specific attributes */ 26 enum dwc_specific_registers { 27 DWC_UFS_REG_HCLKDIV = 0xFC, 28 }; 29 30 /* Clock Divider Values: Hex equivalent of frequency in MHz */ 31 enum clk_div_values { 32 DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e, 33 DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d, 34 DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8, 35 }; 36 37 /* Selector Index */ 38 enum selector_index { 39 SELIND_LN0_TX = 0x00, 40 SELIND_LN1_TX = 0x01, 41 SELIND_LN0_RX = 0x04, 42 SELIND_LN1_RX = 0x05, 43 }; 44 45 struct ufshcd_dme_attr_val { 46 u32 attr_sel; 47 u32 mib_val; 48 u8 peer; 49 }; 50 51 struct ufs_rockchip_host { 52 struct ufs_hba *hba; 53 void __iomem *ufs_phy_ctrl; 54 void __iomem *ufs_sys_ctrl; 55 void __iomem *mphy_base; 56 struct reset_ctl_bulk rsts; 57 struct clk ref_out_clk; 58 uint64_t caps; 59 uint32_t phy_config_mode; 60 bool in_suspend; 61 }; 62 63 #define ufs_sys_writel(base, val, reg) \ 64 writel((val), (base) + (reg)) 65 #define ufs_sys_readl(base, reg) readl((base) + (reg)) 66 #define ufs_sys_set_bits(base, mask, reg) \ 67 ufs_sys_writel((base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg)) 68 #define ufs_sys_ctrl_clr_bits(base, mask, reg) \ 69 ufs_sys_writel((base), ((~(mask)) & (ufs_sys_readl((base), (reg)))), (reg)) 70 71 #endif /* _UFS_ROCKCHIP_H_ */ 72