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Searched refs:tmp2 (Results 1 – 12 of 12) sorted by relevance

/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dnand_ecc.c69 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
98 tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */ in nand_calculate_ecc()
99 tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ in nand_calculate_ecc()
100 tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */ in nand_calculate_ecc()
101 tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ in nand_calculate_ecc()
102 tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */ in nand_calculate_ecc()
103 tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ in nand_calculate_ecc()
104 tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */ in nand_calculate_ecc()
105 tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */ in nand_calculate_ecc()
109 ecc_code[1] = ~tmp2; in nand_calculate_ecc()
/rk3399_rockchip-uboot/lib/
H A Drbtree.c196 struct rb_node *node = NULL, *sibling, *tmp1, *tmp2; in ____rb_erase_color() local
228 tmp2 = sibling->rb_left; in ____rb_erase_color()
229 if (!tmp2 || rb_is_black(tmp2)) { in ____rb_erase_color()
269 sibling->rb_left = tmp1 = tmp2->rb_right; in ____rb_erase_color()
270 tmp2->rb_right = sibling; in ____rb_erase_color()
271 parent->rb_right = tmp2; in ____rb_erase_color()
275 augment_rotate(sibling, tmp2); in ____rb_erase_color()
277 sibling = tmp2; in ____rb_erase_color()
291 parent->rb_right = tmp2 = sibling->rb_left; in ____rb_erase_color()
294 if (tmp2) in ____rb_erase_color()
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H A Daes.c515 u8 tmp0, tmp1, tmp2, tmp3, tmp4; in aes_expand_key() local
523 tmp2 = expkey[4*idx - 2]; in aes_expand_key()
529 tmp1 = sbox[tmp2]; in aes_expand_key()
530 tmp2 = sbox[tmp4]; in aes_expand_key()
534 tmp2 = sbox[tmp2]; in aes_expand_key()
540 expkey[4*idx+2] = expkey[4*idx - 4*AES_KEYCOLS + 2] ^ tmp2; in aes_expand_key()
/rk3399_rockchip-uboot/arch/arm/lib/
H A Ddebug.S26 .macro addruart_current, rx, tmp1, tmp2 argument
27 addruart \tmp1, \tmp2, \rx
31 movne \rx, \tmp2
35 .macro addruart_current, rx, tmp1, tmp2 argument
36 addruart \rx, \tmp1, \tmp2
/rk3399_rockchip-uboot/scripts/
H A Dbuild-whitelist.sh44 |sort |uniq >scripts/config_whitelist.txt.tmp2
47 comm -23 scripts/config_whitelist.txt.tmp1 scripts/config_whitelist.txt.tmp2 \
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c310 u32 tmp2; in serdes_phy_config() local
312 tmp2 = reg_read(CPU_AVS_CONTROL0_REG); in serdes_phy_config()
313 DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2); in serdes_phy_config()
315 tmp2 |= 0x0FF; in serdes_phy_config()
316 reg_write(CPU_AVS_CONTROL0_REG, tmp2); in serdes_phy_config()
317 DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2); in serdes_phy_config()
343 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_phy_config()
345 tmp2); in serdes_phy_config()
346 tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */ in serdes_phy_config()
347 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2); in serdes_phy_config()
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/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_power_init.c467 uint32_t tmp, tmp2; in mxs_power_init_4p2_regulator() local
539 tmp2 = readl(&power_regs->hw_power_5vctrl); in mxs_power_init_4p2_regulator()
540 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; in mxs_power_init_4p2_regulator()
541 tmp2 |= tmp << in mxs_power_init_4p2_regulator()
543 writel(tmp2, &power_regs->hw_power_5vctrl); in mxs_power_init_4p2_regulator()
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c488 u32 tmp1, tmp2, reg; in ddr3_set_performance_params() local
506 tmp2 = (dram_info->wl_max_phase - dram_info->rl_min_phase) / 2 + in ddr3_set_performance_params()
509 trd2wr_wr2rd = (tmp1 >= tmp2) ? tmp1 : tmp2; in ddr3_set_performance_params()
/rk3399_rockchip-uboot/lib/bzip2/
H A Dbzlib_compress.c504 UChar pos[BZ_N_GROUPS], ll_i, tmp2, tmp; in sendMTFValues() local
512 tmp2 = tmp; in sendMTFValues()
514 pos[j] = tmp2; in sendMTFValues()
/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dsmc.c75 u32 tmp1, tmp2; in prog_ddr_timing_control() local
115 tmp2 = wl - 3; in prog_ddr_timing_control()
167 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); in prog_ddr_timing_control()
169 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); in prog_ddr_timing_control()
/rk3399_rockchip-uboot/common/
H A Dedid.c2411 int tmp1, tmp2; in drm_cvt_mode() local
2421 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + in drm_cvt_mode()
2423 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); in drm_cvt_mode()
2478 int tmp1, tmp2; in drm_cvt_mode() local
2482 tmp2 = vdisplay_rnd + 2 * vmargin; in drm_cvt_mode()
2483 hperiod = tmp1 / (tmp2 * vfieldrate); in drm_cvt_mode()
4467 unsigned int tmp1, tmp2; in drm_gtf_mode_complex() local
4513 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * in drm_gtf_mode_complex()
4515 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; in drm_gtf_mode_complex()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3399.c1249 u32 tmp, tmp1, tmp2; in pctl_cfg() local
1309 tmp2 = readl(&denali_phy[922]); in pctl_cfg()
1313 (((tmp2 >> 0) & 0x1) == 0x1)) in pctl_cfg()