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Searched refs:tmp1 (Results 1 – 10 of 10) sorted by relevance

/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dnand_ecc.c69 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
89 tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */ in nand_calculate_ecc()
90 tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ in nand_calculate_ecc()
91 tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */ in nand_calculate_ecc()
92 tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ in nand_calculate_ecc()
93 tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */ in nand_calculate_ecc()
94 tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ in nand_calculate_ecc()
95 tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */ in nand_calculate_ecc()
96 tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ in nand_calculate_ecc()
108 ecc_code[0] = ~tmp1; in nand_calculate_ecc()
/rk3399_rockchip-uboot/lib/
H A Drbtree.c196 struct rb_node *node = NULL, *sibling, *tmp1, *tmp2; in ____rb_erase_color() local
218 parent->rb_right = tmp1 = sibling->rb_left; in ____rb_erase_color()
220 rb_set_parent_color(tmp1, parent, RB_BLACK); in ____rb_erase_color()
224 sibling = tmp1; in ____rb_erase_color()
226 tmp1 = sibling->rb_right; in ____rb_erase_color()
227 if (!tmp1 || rb_is_black(tmp1)) { in ____rb_erase_color()
269 sibling->rb_left = tmp1 = tmp2->rb_right; in ____rb_erase_color()
272 if (tmp1) in ____rb_erase_color()
273 rb_set_parent_color(tmp1, sibling, in ____rb_erase_color()
276 tmp1 = sibling; in ____rb_erase_color()
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H A Daes.c515 u8 tmp0, tmp1, tmp2, tmp3, tmp4; in aes_expand_key() local
522 tmp1 = expkey[4*idx - 3]; in aes_expand_key()
528 tmp0 = sbox[tmp1] ^ rcon[idx / AES_KEYCOLS]; in aes_expand_key()
529 tmp1 = sbox[tmp2]; in aes_expand_key()
533 tmp1 = sbox[tmp1]; in aes_expand_key()
539 expkey[4*idx+1] = expkey[4*idx - 4*AES_KEYCOLS + 1] ^ tmp1; in aes_expand_key()
/rk3399_rockchip-uboot/arch/arm/lib/
H A Ddebug.S26 .macro addruart_current, rx, tmp1, tmp2
27 addruart \tmp1, \tmp2, \rx
30 moveq \rx, \tmp1
35 .macro addruart_current, rx, tmp1, tmp2
36 addruart \rx, \tmp1, \tmp2
/rk3399_rockchip-uboot/scripts/
H A Dbuild-whitelist.sh37 |sort |uniq >scripts/config_whitelist.txt.tmp1;
47 comm -23 scripts/config_whitelist.txt.tmp1 scripts/config_whitelist.txt.tmp2 \
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rv1108_pctl_phy.c417 u32 tmp1 = 0; in data_training() local
424 tmp1 = readl(&priv->phy->phy_reg2); in data_training()
426 writel(DQS_GATE_TRAINING_SEL_CS0 | DQS_GATE_TRAINING_DIS | tmp1, in data_training()
428 writel(DQS_GATE_TRAINING_SEL_CS0 | DQS_GATE_TRAINING_ACT | tmp1, in data_training()
441 writel(DQS_GATE_TRAINING_SEL_CS0 | DQS_GATE_TRAINING_DIS | tmp1, in data_training()
H A Dsdram_rk3399.c1249 u32 tmp, tmp1, tmp2; in pctl_cfg() local
1271 tmp1 = readl(&denali_ctl[14]); in pctl_cfg()
1272 writel(tmp + tmp1, &denali_ctl[14]); in pctl_cfg()
1308 tmp1 = readl(&denali_phy[921]); in pctl_cfg()
1311 (((tmp1 >> 16) & 0x1) == 0x1) && in pctl_cfg()
1312 (((tmp1 >> 0) & 0x1) == 0x1) && in pctl_cfg()
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c488 u32 tmp1, tmp2, reg; in ddr3_set_performance_params() local
503 tmp1 = (dram_info->rl_max_phase - dram_info->wl_min_phase) / 2 + in ddr3_set_performance_params()
509 trd2wr_wr2rd = (tmp1 >= tmp2) ? tmp1 : tmp2; in ddr3_set_performance_params()
/rk3399_rockchip-uboot/common/
H A Dedid.c2411 int tmp1, tmp2; in drm_cvt_mode() local
2419 tmp1 = HV_FACTOR * 1000000 - in drm_cvt_mode()
2423 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); in drm_cvt_mode()
2425 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; in drm_cvt_mode()
2427 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) in drm_cvt_mode()
2430 vsyncandback_porch = tmp1; in drm_cvt_mode()
2478 int tmp1, tmp2; in drm_cvt_mode() local
2480 tmp1 = HV_FACTOR * 1000000 - in drm_cvt_mode()
2483 hperiod = tmp1 / (tmp2 * vfieldrate); in drm_cvt_mode()
4467 unsigned int tmp1, tmp2; in drm_gtf_mode_complex() local
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/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dsmc.c75 u32 tmp1, tmp2; in prog_ddr_timing_control() local
107 tmp1 = tcl - 5; in prog_ddr_timing_control()
167 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); in prog_ddr_timing_control()
169 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); in prog_ddr_timing_control()