Searched refs:tim1 (Results 1 – 1 of 1) sorted by relevance
600 u32 tim1 = 0, val = 0; in get_sdram_tim_1_reg() local602 tim1 |= val << EMIF_REG_T_WTR_SHIFT; in get_sdram_tim_1_reg()610 tim1 |= val << EMIF_REG_T_RRD_SHIFT; in get_sdram_tim_1_reg()613 tim1 |= val << EMIF_REG_T_RC_SHIFT; in get_sdram_tim_1_reg()616 tim1 |= val << EMIF_REG_T_RAS_SHIFT; in get_sdram_tim_1_reg()619 tim1 |= val << EMIF_REG_T_WR_SHIFT; in get_sdram_tim_1_reg()622 tim1 |= val << EMIF_REG_T_RCD_SHIFT; in get_sdram_tim_1_reg()625 tim1 |= val << EMIF_REG_T_RP_SHIFT; in get_sdram_tim_1_reg()627 return tim1; in get_sdram_tim_1_reg()