Home
last modified time | relevance | path

Searched refs:tim (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/
H A Dtimer.c49 struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; in timer_init() local
55 &tim->psc); in timer_init()
58 &tim->psc); in timer_init()
60 writel(0xFFFFFFFF, &tim->arr); in timer_init()
61 writel(TIM_CR1_CEN, &tim->cr1); in timer_init()
62 setbits_le32(&tim->egr, TIM_EGR_UG); in timer_init()
78 struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; in get_ticks() local
81 now = readl(&tim->cnt); in get_ticks()
95 struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; in reset_timer() local
97 gd->arch.lastinc = readl(&tim->cnt); in reset_timer()
/rk3399_rockchip-uboot/drivers/rtc/
H A Dat91sam9_rtt.c37 ulong tim; in rtc_get() local
42 tim = readl(&rtt->vr); in rtc_get()
44 } while (tim!=tim2); in rtc_get()
47 rtc_to_tm(tim+off, tmp); in rtc_get()
55 ulong tim; in rtc_set() local
57 tim = rtc_mktime(tmp); in rtc_set()
62 writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); in rtc_set()
H A Dpl031.c64 unsigned long tim; in rtc_set() local
75 tim = rtc_mktime(tmp); in rtc_set()
77 RTC_WRITE_REG(RTC_LR, tim); in rtc_set()
87 ulong tim; in rtc_get() local
97 tim = RTC_READ_REG(RTC_DR); in rtc_get()
99 rtc_to_tm(tim, tmp); in rtc_get()
H A Dmcfrtc.c31 int tim; in rtc_get() local
37 tim = (rtc_days * 24) + rtc_hrs; in rtc_get()
38 tim = (tim * 60) + rtc_mins; in rtc_get()
39 tim = (tim * 60) + rtc->seconds; in rtc_get()
41 rtc_to_tm(tim, tmp); in rtc_get()
H A Dmc13xxx-rtc.c16 int tim, i = 0; in rtc_get() local
37 tim = day1 * 86400 + time; in rtc_get()
39 rtc_to_tm(tim, rtc); in rtc_get()
H A Ddate.c69 int rtc_to_tm(int tim, struct rtc_time *tm) in rtc_to_tm() argument
74 day = tim / SECDAY; in rtc_to_tm()
75 hms = tim % SECDAY; in rtc_to_tm()
H A Dds1306.c181 ulong tim; in rtc_set() local
183 tim = rtc_mktime(tmp); in rtc_set()
186 immap->im_sit.sit_rtc = tim; in rtc_set()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Drockchip_dmc.c532 struct rk3328_ddr_dts_config_timing *tim) in rk3328_de_skew_setting_2_register() argument
538 memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew)); in rk3328_de_skew_setting_2_register()
539 memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew)); in rk3328_de_skew_setting_2_register()
540 memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew)); in rk3328_de_skew_setting_2_register()
548 tim->ca_skew[offset] &= ~(0xf << shift); in rk3328_de_skew_setting_2_register()
549 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); in rk3328_de_skew_setting_2_register()
561 tim->cs0_skew[offset] &= ~(0xf << shift); in rk3328_de_skew_setting_2_register()
562 tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift); in rk3328_de_skew_setting_2_register()
574 tim->cs1_skew[offset] &= ~(0xf << shift); in rk3328_de_skew_setting_2_register()
575 tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift); in rk3328_de_skew_setting_2_register()
[all …]
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_mxc.c133 u32 tim; member
152 writel(0, &base->tim); in _mxc_serial_init()