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/rk3399_rockchip-uboot/arch/arm/mach-bcmstb/
H A DKconfig8 is acting as the second stage bootloader, and U-Boot is
9 acting as the third stage bootloader (TSBL), loaded by BOLT.
29 hex "Address to which the prior stage provided DTB will be copied"
/rk3399_rockchip-uboot/cmd/
H A Dsf.c400 int stage; member
406 static void show_time(struct test_info *test, int stage) in show_time() argument
412 if (test->time_ms[stage]) in show_time()
413 do_div(speed, test->time_ms[stage] * 1024); in show_time()
416 printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage, in show_time()
417 stage_name[stage], test->time_ms[stage], in show_time()
423 test->time_ms[test->stage] = get_timer(test->base_ms); in spi_test_next_stage()
424 show_time(test, test->stage); in spi_test_next_stage()
426 test->stage++; in spi_test_next_stage()
/rk3399_rockchip-uboot/board/freescale/mpc8536ds/
H A DREADME11 u-boot-nand.bin. This image contains two parts: a first stage image(also
12 call 4K NAND loader and a second stage image. The former is appended to
15 The bootup process can be divided into two stages: the first stage will
16 configure the L2SRAM, then copy the second stage image to L2SRAM and jump
17 to it. The second stage image is to configure all the hardware and boot up
25 second stage image. It's set in the board config file when boot from NAND
/rk3399_rockchip-uboot/doc/uImage.FIT/
H A Dverified-boot.txt76 1. Master private key is used by the signer to sign a first-stage image.
78 2. Secondary private key is created and used to sign second-stage images.
79 3. Secondary public key is placed in first stage images
80 4. We use the master public key to verify the first-stage image. We then
81 use the secondary public key in the first-stage image to verify the second-
84 different key at each stage, so that a compromise in one place will not
/rk3399_rockchip-uboot/tools/buildman/
H A Dfunc_test.py373 def _HandleMake(self, commit, brd, stage, cwd, *args, **kwargs): argument
385 if stage == 'mrproper':
387 elif stage == 'config':
390 elif stage == 'build':
399 print 'make', stage
H A Dtest.py140 def Make(self, commit, brd, stage, *args, **kwargs): argument
154 if stage == 'build':
H A Dbuilderthread.py91 def Make(self, commit, brd, stage, cwd, *args, **kwargs): argument
110 return self.builder.do_make(commit, brd, stage, cwd, *args,
/rk3399_rockchip-uboot/include/
H A Dandroid_bootloader_message.h71 char stage[32]; member
H A Dboot_rkimg.h37 char stage[32]; member
/rk3399_rockchip-uboot/doc/SPL/
H A DREADME.spl-secure-boot13 The SPL image is responsible for loading the next stage boot loader, which is
/rk3399_rockchip-uboot/common/spl/
H A DKconfig34 string "Linker script for the SPL stage"
38 The SPL stage will usually require a different linker-script
40 U-Boot stage. Set this to the path of the linker-script to
54 ROM for loading the next boot-stage after performing basic setup
55 from the SPL stage.
762 Enable support for loading next stage, U-Boot or otherwise, from
1031 string "Linker script for the TPL stage"
1034 The TPL stage will usually require a different linker-script
1036 U-Boot stage. Set this to the path of the linker-script to
1040 fall back to the linker-script used for the SPL stage.
[all …]
/rk3399_rockchip-uboot/doc/
H A DREADME.multi-dtb-fit31 The compression stage is optional but reduces the impact on the size of the
39 during the early initialization stage of the SPL (spl_early_init() or
H A DREADME.N12139 - 8-stage pipeline.
H A DREADME.ti-secure59 XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
89 XIP_X-LOADER - Generates a single stage u-boot for
159 The SPL image is responsible for loading the next stage boot loader,
H A DREADME.drivers.eth38 So the call graph at this stage would look something like:
175 So the call graph at this stage would look something like:
H A DREADME.bcm7xxx5 a third stage bootloader loaded by Broadcom's BOLT bootloader.
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_prv_if.h103 enum hws_result *ddr3_tip_get_result_ptr(u32 stage);
H A Dddr3_training.c2380 u32 if_id, stage, ret; in ddr3_tip_ddr3_auto_tune() local
2386 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++) in ddr3_tip_ddr3_auto_tune()
2387 training_result[stage][if_id] = NO_TEST_DONE; in ddr3_tip_ddr3_auto_tune()
2410 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++) { in ddr3_tip_ddr3_auto_tune()
2411 if (training_result[stage][if_id] == TEST_FAILED) in ddr3_tip_ddr3_auto_tune()
H A Dddr3_training_leveling.c1429 wr_supp_res[if_id][bus_id].stage = PHASE_SHIFT; in ddr3_tip_wl_supp_align_phase_shift()
1438 wr_supp_res[if_id][bus_id].stage = CLOCK_SHIFT; in ddr3_tip_wl_supp_align_phase_shift()
1452 wr_supp_res[if_id][bus_id].stage = ALIGN_SHIFT; in ddr3_tip_wl_supp_align_phase_shift()
1831 [bus_id].stage)); in ddr3_tip_print_wl_supp_result()
/rk3399_rockchip-uboot/board/qualcomm/dragonboard410c/
H A Dreadme.txt48 Later on proper device tree is passed to next boot stage.
/rk3399_rockchip-uboot/board/theobroma-systems/lion_rk3368/
H A DREADME17 Build the TPL/SPL stage
/rk3399_rockchip-uboot/doc/device-tree-bindings/
H A Dchosen.txt48 In a system using an SPL stage and having multiple boot sources
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig140 which is loaded during boot stage, and then remains resident in RAM
152 which is loaded during boot stage, and then remains resident in RAM
154 stage instead of the RAM version of U-Boot. Once PPA is initialized,
/rk3399_rockchip-uboot/doc/driver-model/
H A Dfdt-fixup.txt60 we have the pre-relocation driver model at our disposal at this stage, which
130 but has not been tested at this stage.
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A DKconfig885 first stage in segments and enter multiple times. E.g. on
886 the RK3188, the first 1KB of the first stage are loaded
888 remainder of the first stage is loaded, but the BROM
891 This enables support code in the BOOT0 hook for the SPL stage
899 first stage in segments and enter multiple times. E.g. on
900 the RK3188, the first 1KB of the first stage are loaded
902 remainder of the first stage is loaded, but the BROM
905 This enables support code in the BOOT0 hook for the TPL stage
1055 is set. This makes U-Boot stage more stable but not flexible any more to

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