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Searched refs:sor (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Dsor.c51 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) in tegra_sor_readl() argument
53 return readl((u32 *)sor->base + reg); in tegra_sor_readl()
56 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, in tegra_sor_writel() argument
59 writel(val, (u32 *)sor->base + reg); in tegra_sor_writel()
62 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, in tegra_sor_write_field() argument
65 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field()
68 tegra_sor_writel(sor, reg, reg_val); in tegra_sor_write_field()
73 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dp_disable_tx_pu() local
75 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dp_disable_tx_pu()
82 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dp_set_pe_vs_pc() local
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H A Ddp.c35 struct udevice *sor; member
720 struct udevice *sor, int ena) in tegra_dc_dp_set_assr() argument
734 tegra_dc_sor_set_internal_panel(sor, ena); in tegra_dc_dp_set_assr()
739 struct udevice *sor, in tegra_dp_set_link_bandwidth() argument
742 tegra_dc_sor_set_link_bandwidth(sor, link_bw); in tegra_dp_set_link_bandwidth()
750 struct udevice *sor) in tegra_dp_set_lane_count() argument
763 tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); in tegra_dp_set_lane_count()
922 tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg); in tegra_dp_tpg()
961 ret = tegra_dc_dp_set_assr(dp, dp->sor, 1); in tegra_dp_link_config()
966 ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw); in tegra_dp_link_config()
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H A DMakefile9 obj-y += sor.o
H A Dsor.h879 int tegra_dc_sor_enable_dp(struct udevice *sor,
881 int tegra_dc_sor_set_power_state(struct udevice *sor, int pu_pd);
886 void tegra_dc_sor_set_panel_power(struct udevice *sor,
893 void tegra_dc_sor_power_down_unused_lanes(struct udevice *sor,
895 int tegra_dc_sor_set_voltage_swing(struct udevice *sor,
899 void tegra_dp_disable_tx_pu(struct udevice *sor);
903 int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *sor,
906 int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *sor);
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dtegra210.dtsi213 sor@54540000 {
214 compatible = "nvidia,tegra210-sor";
221 clock-names = "sor", "parent", "dp", "safe";
223 reset-names = "sor";
227 sor@54580000 {
235 clock-names = "sor", "parent", "dp", "safe";
237 reset-names = "sor";
H A Dtegra124.dtsi139 sor@54540000 {
140 compatible = "nvidia,tegra124-sor";
147 clock-names = "sor", "parent", "dp", "safe";
149 reset-names = "sor";
H A Dtegra124-nyan.dtsi28 sor@54540000 {
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt195 - sor: serial output resource
198 - compatible: "nvidia,tegra124-sor"
204 - sor: clock input for the SOR hardware
211 - sor
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dzynq_nand.c115 u32 sor; /* 0x18 */ member
281 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor); in zynq_nand_init_nand_flash()
283 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor); in zynq_nand_init_nand_flash()