Searched refs:read_aux_reg (Results 1 – 5 of 5) sorted by relevance
54 reg = read_aux_reg(ARC_AUX_SLC_CTRL); in __before_slc_op()68 read_aux_reg(ARC_AUX_SLC_CTRL); in __after_slc_op()69 while (read_aux_reg(ARC_AUX_SLC_CTRL) & in __after_slc_op()152 sbcr.word = read_aux_reg(ARC_BCR_SLC); in read_decode_cache_bcr_arcv2()154 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); in read_decode_cache_bcr_arcv2()170 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); in read_decode_cache_bcr_arcv2()191 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); in read_decode_cache_bcr()199 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); in read_decode_cache_bcr()255 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) in icache_status()264 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & in icache_enable()[all …]
25 int status = read_aux_reg(ARC_AUX_STATUS32); in disable_interrupts()36 unsigned int status = read_aux_reg(ARC_AUX_STATUS32); in enable_interrupts()
37 val = read_aux_reg(ARC_AUX_TIMER0_CNT); in arc_timer_get_count()40 val = read_aux_reg(ARC_AUX_TIMER1_CNT); in arc_timer_get_count()
70 #define read_aux_reg(reg) __builtin_arc_lr(reg) macro
82 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; in smp_kick_all_cpus()