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Searched refs:pll_p (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/
H A Dclock.c87 u8 pll_p; member
119 .pll_p = 2,
130 .pll_p = 2,
169 | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) in configure_clocks()
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_stm32f7.c65 u8 pll_p; member
101 .pll_p = 2,
142 pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; in configure_clocks()
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt152 121 pll_p
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dtegra124.dtsi990 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";