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Searched refs:pll_ddr (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/
H A Dclock.c156 reg = readl(&ccm_anatop->pll_ddr); in decode_pll()
345 reg = readl(&ccm_anatop->pll_ddr); in mxc_get_pll_ddr_derive()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h91 uint32_t pll_ddr; /* offset 0x0070 */ member