Searched refs:pll_cr0 (Results 1 – 1 of 1) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | fsl_corenet2_serdes.c | 206 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; in serdes_init() local
276 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
278 pll_cr0 | (dc << CR0_DCBIAS_SHIFT)); in serdes_init()
280 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT))); in serdes_init()
303 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
304 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 | in serdes_init()
310 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
311 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 & in serdes_init()
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