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Searched refs:pll_con1 (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/exynos/
H A Dclk-pll.c22 unsigned long pll_con1 = readl(con1); in pll145x_get_rate() local
26 mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; in pll145x_get_rate()
27 pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; in pll145x_get_rate()
28 sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; in pll145x_get_rate()