Searched refs:i2c_base (Results 1 – 8 of 8) sorted by relevance
| /rk3399_rockchip-uboot/drivers/i2c/ |
| H A D | davinci_i2c.c | 35 REG(&(i2c_base->i2c_con)) = 0;\
40 static int _wait_for_bus(struct i2c_regs *i2c_base) in _wait_for_bus() argument
44 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
47 stat = REG(&(i2c_base->i2c_stat)); in _wait_for_bus()
49 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
53 REG(&(i2c_base->i2c_stat)) = stat; in _wait_for_bus()
57 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
61 static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask) in _poll_i2c_irq() argument
67 stat = REG(&(i2c_base->i2c_stat)); in _poll_i2c_irq()
72 REG(&(i2c_base->i2c_stat)) = 0xffff; in _poll_i2c_irq()
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| H A D | omap24xx_i2c.c | 119 static int wait_for_bb(struct i2c *i2c_base, int waitdelay) argument
124 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
126 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
129 while ((stat = readw(&i2c_base->irqstatus_raw) &
132 writew(stat, &i2c_base->stat);
141 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
149 static u16 wait_for_event(struct i2c *i2c_base, int waitdelay) argument
157 status = readw(&i2c_base->stat);
160 status = readw(&i2c_base->irqstatus_raw);
175 writew(0xFFFF, &i2c_base->stat);
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| H A D | designware_i2c.c | 40 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) in dw_i2c_enable() argument
44 writel(ena, &i2c_base->ic_enable); in dw_i2c_enable()
47 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) in dw_i2c_enable() argument
53 writel(ena, &i2c_base->ic_enable); in dw_i2c_enable()
54 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) in dw_i2c_enable()
75 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, in __dw_i2c_set_bus_speed() argument
91 dw_i2c_enable(i2c_base, false); in __dw_i2c_set_bus_speed()
93 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); in __dw_i2c_set_bus_speed()
106 writel(hcnt, &i2c_base->ic_hs_scl_hcnt); in __dw_i2c_set_bus_speed()
107 writel(lcnt, &i2c_base->ic_hs_scl_lcnt); in __dw_i2c_set_bus_speed()
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| H A D | fsl_i2c.c | 40 static const struct fsl_i2c_base *i2c_base[4] = { variable
500 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd, in fsl_i2c_init()
507 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); in fsl_i2c_probe_chip()
515 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], in fsl_i2c_read()
524 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], in fsl_i2c_write()
531 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, in fsl_i2c_set_bus_speed()
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| /rk3399_rockchip-uboot/board/samsung/smdk5420/ |
| H A D | smdk5420_spl.c | 39 .i2c_base = 0x12c60000,
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| /rk3399_rockchip-uboot/board/samsung/arndale/ |
| H A D | arndale_spl.c | 37 .i2c_base = 0x12c60000,
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| /rk3399_rockchip-uboot/board/samsung/smdk5250/ |
| H A D | smdk5250_spl.c | 39 .i2c_base = 0x12c60000,
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/ |
| H A D | spl.h | 56 u32 i2c_base; /* i2c base address */ member
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