Searched refs:gctrl (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/drivers/video/sunxi/ |
| H A D | tve_common.c | 22 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl); in tvencoder_mode_set() 34 SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl); in tvencoder_mode_set() 60 SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl); in tvencoder_mode_set() 85 setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE); in tvencoder_enable()
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| /rk3399_rockchip-uboot/board/renesas/sh7757lcr/ |
| H A D | sh7757lcr.c | 24 struct gctrl_regs *gctrl = GCTRL_BASE; in init_gctrl() local 28 writel(graofst | 0x20000f00, &gctrl->gracr3); in init_gctrl() 317 struct gctrl_regs *gctrl = GCTRL_BASE; in finish_spiboot() local 324 writel(0x00000000, &gctrl->spibootcan); in finish_spiboot() 339 struct gctrl_regs *gctrl = GCTRL_BASE; in do_sh_g200() local 342 writel(0xfedcba98, &gctrl->wprotect); in do_sh_g200() 344 writel(graofst | 0xa0000f00, &gctrl->gracr3); in do_sh_g200()
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| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | sunxi_mmc.c | 263 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); in sunxi_mmc_core_init() 284 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); in mmc_trans_data_by_cpu() 433 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); in sunxi_mmc_send_cmd_common() 437 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, in sunxi_mmc_send_cmd_common() 438 &priv->reg->gctrl); in sunxi_mmc_send_cmd_common() 616 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); in sunxi_mmc_probe()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | mmc.h | 17 u32 gctrl; /* 0x00 global control */ member
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| H A D | tve.h | 29 u32 gctrl; /* 0x000 */ member
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