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Searched refs:final_delay (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dsmc.c1417 uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES]; in rcvn_cal() local
1447 memset((void *)(final_delay), 0x00, (size_t)sizeof(final_delay)); in rcvn_cal()
1515 final_delay[ch][bl] += delay[bl]; in rcvn_cal()
1517 set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rcvn_cal()
1564 uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES]; in wr_level() local
1593 memset((void *)(final_delay), 0x00, (size_t)sizeof(final_delay)); in wr_level()
1743 final_delay[ch][bl] += delay[bl]; in wr_level()
1744 set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in wr_level()
1746 set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); in wr_level()
1813 uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES]; in rd_train() local
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/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c338 int *counter_in_progress, int final_delay, u32 delay, in overrun() argument
342 if (((~locked_pups >> pup) & 0x1) && (final_delay == 0)) { in overrun()
408 int final_delay = 0; in ddr3_read_leveling_single_cs_rl_mode() local
473 &counter_in_progress, final_delay, in ddr3_read_leveling_single_cs_rl_mode()
536 final_delay = 1; in ddr3_read_leveling_single_cs_rl_mode()
760 int final_delay = 0; in ddr3_read_leveling_single_cs_window_mode() local
840 && (final_delay == 0)) { in ddr3_read_leveling_single_cs_window_mode()
960 final_delay = 1; in ddr3_read_leveling_single_cs_window_mode()