1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wenping Zhang <wenping.zhang@rock-chips.com>
6 */
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <dm/pinctrl.h>
11 #include <pwm.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <asm/arch/clock.h>
15 #include <asm/io.h>
16 #include <syscon.h>
17 #include <linux/io.h>
18 #include "rk_ebc.h"
19 #ifdef CONFIG_IRQ
20 #include <irq-generic.h>
21 #endif
22
23 struct ebc_tcon_priv {
24 struct udevice *dev;
25 void __iomem *reg;
26 u32 *regcache;
27 u32 reg_len;
28 void *grf;
29 void *pmugrf;
30 struct clk dclk;
31 };
32
33 #define msleep(a) udelay((a) * 1000)
34 #define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16))
35 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
36
37 #define REG_LOAD_GLOBAL_EN 0x1
38
39 /* ebc register define */
40 #define EBC_DSP_START 0x0000 //Frame statrt register
41 #define EBC_EPD_CTRL 0x0004 //EPD control register
42 #define EBC_DSP_CTRL 0x0008 //Display control register
43 #define EBC_DSP_HTIMING0 0x000c //H-Timing setting register0
44 #define EBC_DSP_HTIMING1 0x0010 //H-Timing setting register1
45 #define EBC_DSP_VTIMING0 0x0014 //V-Timing setting register0
46 #define EBC_DSP_VTIMING1 0x0018 //V-Timing setting register1
47 #define EBC_DSP_ACT_INFO 0x001c //ACTIVE width/height
48 #define EBC_WIN_CTRL 0x0020 //Window ctrl
49 #define EBC_WIN_MST0 0x0024 //Current win memory start
50 #define EBC_WIN_MST1 0x0028 //Next win memory start
51 #define EBC_WIN_VIR 0x002c //Window vir width/height
52 #define EBC_WIN_ACT 0x0030 //Window act width/height
53 #define EBC_WIN_DSP 0x0034 //Window dsp width/height
54 #define EBC_WIN_DSP_ST 0x0038 //Window display start point
55 #define EBC_INT_STATUS 0x003c //Interrupt register
56 #define EBC_VCOM0 0x0040 //VCOM setting register0
57 #define EBC_VCOM1 0x0044 //VCOM setting register1
58 #define EBC_VCOM2 0x0048 //VCOM setting register2
59 #define EBC_VCOM3 0x004c //VCOM setting register3
60 #define EBC_CONFIG_DONE 0x0050 //Config done register
61 #define EBC_VNUM 0x0054 //Line flag num
62 #define EBC_WIN_MST2 0x0058 //Framecount memory start
63 #define EBC_LUT_DATA_ADDR 0x1000 //lut data address
64
65 #define DSP_HTOTAL(x) UPDATE(x, 27, 16)
66 #define DSP_HS_END(x) UPDATE(x, 7, 0)
67 #define DSP_HACT_END(x) UPDATE(x, 26, 16)
68 #define DSP_HACT_ST(x) UPDATE(x, 7, 0)
69 #define DSP_VTOTAL(x) UPDATE(x, 26, 16)
70 #define DSP_VS_END(x) UPDATE(x, 7, 0)
71 #define DSP_VACT_END(x) UPDATE(x, 26, 16)
72 #define DSP_VACT_ST(x) UPDATE(x, 7, 0)
73 #define DSP_HEIGHT(x) UPDATE(x, 26, 16)
74 #define DSP_WIDTH(x) UPDATE(x, 11, 0)
75
76 #define WIN2_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 27, 19)
77 #define WIN_EN(x) UPDATE(x, 18, 18)
78 #define BURST_REG(x) UPDATE(x, 12, 10)
79 #define WIN_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 9, 2)
80 #define WIN_FMT(x) UPDATE(x, 1, 0)
81
82 #define WIN_VIR_HEIGHT(x) UPDATE(x, 31, 16)
83 #define WIN_VIR_WIDTH(x) UPDATE(x, 15, 0)
84 #define WIN_ACT_HEIGHT(x) UPDATE(x, 26, 16)
85 #define WIN_ACT_WIDTH(x) UPDATE(x, 11, 0)
86 #define WIN_DSP_HEIGHT(x) UPDATE(x, 26, 16)
87 #define WIN_DSP_WIDTH(x) UPDATE(x, 11, 0)
88 #define WIN_DSP_YST(x) UPDATE(x, 26, 16)
89 #define WIN_DSP_XST(x) UPDATE(x, 11, 0)
90
91 #define DSP_OUT_LOW BIT(31)
92 #define DSP_EINK_MODE(x) UPDATE(x, 13, 13)
93 #define DSP_EINK_MODE_MASK BIT(13)
94 #define DSP_SDCE_WIDTH(x) UPDATE(x, 25, 16)
95 #define DSP_FRM_TOTAL(x) UPDATE(x, 9, 2)
96 #define DSP_FRM_TOTAL_MASK GENMASK(9, 2)
97 #define DSP_FRM_START BIT(0)
98 #define DSP_FRM_START_MASK BIT(0)
99 #define SW_BURST_CTRL BIT(12)
100
101 #define EINK_MODE_SWAP(x) UPDATE(x, 31, 31)
102 #define EINK_MODE_FRM_SEL(x) UPDATE(x, 30, 30)
103 #define DSP_GD_END(x) UPDATE(x, 26, 16)
104 #define DSP_GD_ST(x) UPDATE(x, 15, 8)
105 #define DSP_THREE_WIN_MODE(x) UPDATE(x, 7, 7)
106 #define THREE_WIN_MODE_MASK BIT(7)
107 #define DSP_SDDW_MODE(x) UPDATE(x, 6, 6)
108 #define EPD_AUO(x) UPDATE(x, 5, 5)
109 #define EPD_PWR(x) UPDATE(x, 4, 2)
110 #define EPD_GDRL(x) UPDATE(x, 1, 1)
111 #define EPD_SDSHR(x) UPDATE(x, 0, 0)
112
113 #define DSP_SWAP_MODE(x) UPDATE(x, 31, 30)
114 #define DSP_SWAP_MODE_MASK GENMASK(31, 30)
115 #define DSP_SDCLK_DIV(x) UPDATE(x, 19, 16)
116 #define DSP_SDCLK_DIV_MASK GENMASK(19, 16)
117 #define DSP_VCOM_MODE(x) UPDATE(x, 27, 27)
118 #define DSP_VCOM_MODE_MASK BIT(27)
119
120 #define DSP_UPDATE_MODE(x) UPDATE(x, 29, 29)
121 #define DSP_DISPLAY_MODE(x) UPDATE(x, 28, 28)
122 #define UPDATE_MODE_MASK BIT(29)
123 #define DISPLAY_MODE_MASK BIT(28)
124
125 #define DSP_FRM_INT_NUM(x) UPDATE(x, 19, 12)
126 #define FRM_END_INT BIT(0)
127 #define DSP_END_INT BIT(1)
128 #define DSP_FRM_INT BIT(2)
129 #define LINE_FLAG_INT BIT(3)
130 #define FRM_END_INT_MASK BIT(4)
131 #define DSP_END_INT_MASK BIT(5)
132 #define DSP_FRM_INT_MASK BIT(6)
133 #define LINE_FLAG_INT_MASK BIT(7)
134 #define FRM_END_INT_CLR BIT(8)
135 #define DSP_END_INT_CLR BIT(9)
136 #define DSP_FRM_INT_CLR BIT(10)
137 #define LINE_FLAG_INT_CLR BIT(11)
138
139 #define RK3576_EBC_DSP_START 0x0000
140 #define RK3576_EBC_EPD_CTRL 0x0004
141 #define RK3576_EBC_DSP_CTRL 0x0008
142 #define RK3576_EBC_DSP_HTIMING0 0x000C
143 #define RK3576_EBC_DSP_HTIMING1 0x0010
144 #define RK3576_EBC_DSP_VTIMING0 0x0014
145 #define RK3576_EBC_DSP_VTIMING1 0x0018
146 #define RK3576_EBC_DSP_ACT_INFO 0x001C
147 #define RK3576_EBC_WIN_CTRL 0x0020
148 #define RK3576_EBC_WIN_MST0 0x0024
149 #define RK3576_EBC_WIN_MST1 0x0028
150 #define RK3576_EBC_WIN_VIR 0x002C
151 #define RK3576_EBC_WIN_ACT 0x0030
152 #define RK3576_EBC_WIN_DSP 0x0034
153 #define RK3576_EBC_WIN_DSP_ST 0x0038
154 #define RK3576_EBC_INT_STATUS 0x003C
155 #define RK3576_EBC_VCOM0 0x0040
156 #define RK3576_EBC_VCOM1 0x0044
157 #define RK3576_EBC_VCOM2 0x0048
158 #define RK3576_EBC_VCOM3 0x004C
159 #define RK3576_EBC_CONFIG_DONE 0x0050
160 #define RK3576_EBC_VNUM 0x0054
161 #define RK3576_EBC_WIN_MST2 0x0058
162 #define RK3576_EBC_DSP_CTRL2 0x005C
163 #define RK3576_EBC_DSP_CTRL3 0x0060
164 #define RK3576_EBC_WIN0_CTRL 0x0064
165 #define RK3576_EBC_WIN1_CTRL 0x0068
166 #define RK3576_EBC_WIN2_CTRL 0x006C
167 #define RK3576_EBC_SYS_CTRL 0x0070
168 #define RK3576_EBC_LUT_ADDRESS_MAP_0 0x1000
169
170 #define RK3576_DSP_FRM_START BIT(0)
171 #define RK3576_DSP_FRM_START_MASK BIT(0)
172
173 #define RK3576_EINK_MODE_SWAP(x) UPDATE(x, 31, 31)
174 #define RK3576_EINK_MODE_FRM_SEL(x) UPDATE(x, 30, 30)
175 #define RK3576_DSP_THREE_WIN_MODE(x) UPDATE(x, 29, 29)
176 #define RK3576_THREE_WIN_MODE_MASK BIT(29)
177 #define RK3576_DSP_GD_END(x) UPDATE(x, 26, 16)
178 #define RK3576_DSP_GD_ST(x) UPDATE(x, 15, 8)
179 #define RK3576_DSP_SDDW_MODE(x) UPDATE(x, 7, 6)
180 #define RK3576_EPD_AUO(x) UPDATE(x, 5, 5)
181 #define RK3576_EPD_PWR(x) UPDATE(x, 4, 2)
182 #define RK3576_EPD_GDRL(x) UPDATE(x, 1, 1)
183 #define RK3576_EPD_SDSHR(x) UPDATE(x, 0, 0)
184
185 #define RK3576_DSP_SWAP_MODE(x) UPDATE(x, 31, 30)
186 #define RK3576_DSP_UPDATE_MODE(x) UPDATE(x, 29, 29)
187 #define RK3576_DSP_DISPLAY_MODE(x) UPDATE(x, 28, 28)
188 #define RK3576_UPDATE_MODE_MASK BIT(29)
189 #define RK3576_DISPLAY_MODE_MASK BIT(28)
190 #define RK3576_DSP_VCOM_MODE(x) UPDATE(x, 27, 27)
191 #define RK3576_DSP_SDCLK_DIV(x) UPDATE(x, 19, 16)
192 #define RK3576_DSP_SDCLK_DIV_MASK GENMASK(19, 16)
193 #define RK3576_DSP_SDOE_MODE(x) UPDATE(x, 0, 0)
194
195 #define RK3576_DSP_HTOTAL(x) UPDATE(x, 31, 16)
196 #define RK3576_DSP_HS_END(x) UPDATE(x, 15, 0)
197 #define RK3576_DSP_HACT_END(x) UPDATE(x, 31, 16)
198 #define RK3576_DSP_HACT_ST(x) UPDATE(x, 15, 0)
199 #define RK3576_DSP_VTOTAL(x) UPDATE(x, 31, 16)
200 #define RK3576_DSP_VS_END(x) UPDATE(x, 15, 0)
201 #define RK3576_DSP_VACT_END(x) UPDATE(x, 31, 16)
202 #define RK3576_DSP_VACT_ST(x) UPDATE(x, 15, 0)
203 #define RK3576_DSP_HEIGHT(x) UPDATE(x, 31, 16)
204 #define RK3576_DSP_WIDTH(x) UPDATE(x, 15, 0)
205
206 #define RK3576_WIN_VIR_HEIGHT(x) UPDATE(x, 31, 16)
207 #define RK3576_WIN_VIR_WIDTH(x) UPDATE(x, 15, 0)
208 #define RK3576_WIN_ACT_HEIGHT(x) UPDATE(x, 31, 16)
209 #define RK3576_WIN_ACT_WIDTH(x) UPDATE(x, 15, 0)
210 #define RK3576_WIN_DSP_HEIGHT(x) UPDATE(x, 31, 16)
211 #define RK3576_WIN_DSP_WIDTH(x) UPDATE(x, 15, 0)
212 #define RK3576_WIN_DSP_YST(x) UPDATE(x, 31, 16)
213 #define RK3576_WIN_DSP_XST(x) UPDATE(x, 15, 0)
214
215 #define RK3576_DMA_BURST_LENGTH(x) UPDATE(x, 25, 24)
216 #define RK3576_WIN2_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 20, 12)
217 #define RK3576_WIN_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 11, 4)
218 #define RK3576_WIN_FMT(x) UPDATE(x, 2, 0)
219 #define RK3576_WIN_FMT_MASK GENMASK(2, 0)
220
221 #define RK3576_WIN_RID(x) UPDATE(x, 7, 4)
222 #define RK3576_WIN_AXI_GATHER_NUM(x) UPDATE(x, 11, 8)
223 #define RK3576_WIN_AXI_GATHER_EN BIT(1)
224 #define RK3576_WIN_EN BIT(0)
225
226 #define RK3576_WIN2_EMPTY_INT_MASK BIT(26)
227 #define RK3576_WIN1_EMPTY_INT_MASK BIT(25)
228 #define RK3576_WIN0_EMPTY_INT_MASK BIT(24)
229 #define RK3576_FRM_END_INT_MASK BIT(4)
230 #define RK3576_DSP_FRM_INT_MASK BIT(6)
231 #define RK3576_LINE_FLAG_INT_MASK BIT(7)
232
233 #define RK3576_DSP_SDCE_WIDTH(x) UPDATE(x, 23, 12)
234 #define RK3576_DSP_SDCE_WIDTH_MASK(x) GENMASK(x, 23, 12)
235 #define RK3576_DSP_FRM_TOTAL(x) UPDATE(x, 11, 4)
236 #define RK3576_DSP_FRM_TOTAL_MASK GENMASK(11, 4)
237 #define RK3576_DSP_EINK_MODE(x) UPDATE(x, 2, 2)
238 #define RK3576_DSP_EINK_MODE_MASK BIT(2)
239 #define RK3576_SW_BURST_CTRL BIT(1)
240 #define RK3576_DSP_OUT_LOW BIT(0)
241
242 #define RK3576_SW_AXI_RD_URGENCY_EN BIT(24)
243 #define RK3576_SW_AXI_MAX_OUTSTAND_NUM(x) UPDATE(x, 20, 16)
244 #define RK3576_SW_AXI_MAX_OUTSTAND_EN BIT(12)
245 #define RK3576_SW_NOC_HURRY_THRESHOLD(x) UPDATE(x, 11, 8)
246 #define RK3576_SW_NOC_HURRY_VALUE(x) UPDATE(x, 6, 5)
247 #define RK3576_SW_NOC_HURRY_EN BIT(4)
248 #define RK3576_SW_NOC_QOS_VALUE(x) UPDATE(x, 2, 1)
249 #define RK3576_SW_NOC_QOS_EN BIT(0)
250
251 #define PMU_BASE_ADDR 0xfdd90000
252 #define PMU_PWR_GATE_SFTCON 0xA0
253 #define PMU_PWR_DWN_ST 0x98
254 #define RGA_PD_OFF BIT(5)
255 #define RGA_PD_STAT BIT(5)
256 enum ebc_win_data_fmt {
257 Y_DATA_4BPP = 0,
258 Y_DATA_8BPP = 1,
259 RGB888 = 2,
260 RGB565 = 3,
261 };
262
263 static volatile int last_frame_done = -1;
regs_dump(struct ebc_tcon_priv * tcon)264 static inline void regs_dump(struct ebc_tcon_priv *tcon)
265 {
266 int i;
267
268 printf("dump registers:\n");
269 for (i = 0; i <= EBC_WIN_MST2; i = i + 4) {
270 if (!(i % 16))
271 printf("\n 0x%p:\t", tcon->reg + i);
272 printf("0x%x\t", readl(tcon->reg + i));
273 }
274 printf("\nlut data:\n");
275 for (i = 0x1000; i <= 0x1100; i = i + 4) {
276 if (!(i % 16))
277 printf("\n 0x%p:\t", tcon->reg + i);
278 printf("0x%x\t", readl(tcon->reg + i));
279 }
280 printf("\n");
281 }
282
283 /* RK356X ebc power domain is enabled by default when power up */
ebc_power_domain(int on)284 static int __maybe_unused ebc_power_domain(int on)
285 {
286 u32 pd_reg;
287 u32 pd_stat;
288 int delay = 0;
289
290 if (on) {
291 pd_reg = RGA_PD_OFF << 16;
292 pd_stat = RGA_PD_STAT;
293 } else {
294 pd_reg = RGA_PD_OFF | (RGA_PD_OFF << 16);
295 pd_stat = ~((u32)RGA_PD_STAT);
296 }
297
298 /* enable rga pd for ebc tcon*/
299 writel(pd_reg, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
300 delay = 1000;
301 do {
302 udelay(1);
303 delay--;
304 if (delay == 0) {
305 printf("Enable rga pd for ebc failed !\n");
306 return -1;
307 }
308 } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & pd_stat);
309
310 return 0;
311 }
312
tcon_write(struct ebc_tcon_priv * tcon,unsigned int reg,unsigned int value)313 static inline void tcon_write(struct ebc_tcon_priv *tcon, unsigned int reg,
314 unsigned int value)
315 {
316 unsigned int *cache = tcon->regcache + (reg >> 2);
317
318 writel(value, tcon->reg + reg);
319 *cache = value;
320 }
321
tcon_read(struct ebc_tcon_priv * tcon,unsigned int reg)322 static inline unsigned int tcon_read(struct ebc_tcon_priv *tcon,
323 unsigned int reg)
324 {
325 return readl(tcon->reg + reg);
326 }
327
tcon_update_bits(struct ebc_tcon_priv * tcon,unsigned int reg,unsigned int mask,unsigned int val)328 static inline void tcon_update_bits(struct ebc_tcon_priv *tcon,
329 unsigned int reg, unsigned int mask,
330 unsigned int val)
331 {
332 unsigned int tmp;
333 unsigned int *cache = tcon->regcache + (reg >> 2);
334
335 tmp = *cache & ~mask;
336 tmp |= val & mask;
337
338 writel(tmp, tcon->reg + reg);
339 *cache = tmp;
340 }
341
342 #ifdef CONFIG_IRQ
ebc_irq_handler(int irq,void * data)343 static void ebc_irq_handler(int irq, void *data)
344 {
345 u32 intr_status;
346 struct udevice *dev = data;
347 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
348
349 intr_status = readl(tcon->reg + EBC_INT_STATUS);
350
351 if (intr_status & DSP_END_INT) {
352 tcon_update_bits(tcon, EBC_INT_STATUS,
353 DSP_END_INT_CLR, DSP_END_INT_CLR);
354 last_frame_done = 1;
355 }
356 }
357 #endif
358
tcon_cfg_done(struct ebc_tcon_priv * tcon)359 static inline void tcon_cfg_done(struct ebc_tcon_priv *tcon)
360 {
361 writel(REG_LOAD_GLOBAL_EN, tcon->reg + EBC_CONFIG_DONE);
362 }
363
364 #ifdef CONFIG_ROCKCHIP_RK3568
ebc_tcon_enable(struct udevice * dev,struct ebc_panel * panel)365 static int ebc_tcon_enable(struct udevice *dev, struct ebc_panel *panel)
366 {
367 int ret;
368 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
369 u32 width, height, vir_width, vir_height;
370
371 if (panel->rearrange) {
372 width = panel->width * 2;
373 height = panel->height / 2;
374 vir_width = panel->vir_width * 2;
375 vir_height = panel->vir_height / 2;
376 } else {
377 width = panel->width;
378 height = panel->height;
379 vir_width = panel->vir_width;
380 vir_height = panel->vir_height;
381 }
382
383 /* panel timing and win info config */
384 tcon_write(tcon, EBC_DSP_HTIMING0,
385 DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl +
386 panel->lel) | DSP_HS_END(panel->lsl));
387 tcon_write(tcon, EBC_DSP_HTIMING1,
388 DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) |
389 DSP_HACT_ST(panel->lsl + panel->lbl - 1));
390 tcon_write(tcon, EBC_DSP_VTIMING0,
391 DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl +
392 panel->fel) | DSP_VS_END(panel->fsl));
393 tcon_write(tcon, EBC_DSP_VTIMING1,
394 DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) |
395 DSP_VACT_ST(panel->fsl + panel->fbl));
396 tcon_write(tcon, EBC_DSP_ACT_INFO,
397 DSP_HEIGHT(vir_height) |
398 DSP_WIDTH(vir_width));
399 tcon_write(tcon, EBC_WIN_VIR,
400 WIN_VIR_HEIGHT(height) |
401 WIN_VIR_WIDTH(width));
402 tcon_write(tcon, EBC_WIN_ACT,
403 WIN_ACT_HEIGHT(height) |
404 WIN_ACT_WIDTH(width));
405 tcon_write(tcon, EBC_WIN_DSP,
406 WIN_DSP_HEIGHT(height) |
407 WIN_DSP_WIDTH(width));
408 tcon_write(tcon, EBC_WIN_DSP_ST,
409 WIN_DSP_YST(panel->fsl + panel->fbl) |
410 WIN_DSP_XST(panel->lsl + panel->lbl));
411
412 /* win2 fifo is 512x128, win fifo is 256x128,
413 * we set fifo almost value (fifo_size - 16)
414 * burst_reg = 7 mean ahb burst is incr16
415 */
416 tcon_write(tcon, EBC_WIN_CTRL,
417 WIN2_FIFO_ALMOST_FULL_LEVEL(496) | WIN_EN(1) |
418 BURST_REG(7) | WIN_FIFO_ALMOST_FULL_LEVEL(240) |
419 WIN_FMT(Y_DATA_4BPP));
420
421 /*
422 * EBC_EPD_CTRL info:
423 * DSP_GD_ST: GCLK rising edge point(SCLK), which count from
424 * the rasing edge of hsync(spec is wrong, count
425 * from rasing edge of hsync, not falling edge of hsync)
426 * DSP_GD_END : GCLK falling edge point(SCLK), which count from
427 * the rasing edge of hsync
428 * DSP_THREE_WIN_MODE: 0: lut mode or direct mode; 1: three win mode
429 * DSP_SDDW_MODE: 0: 8 bit data output; 1: 16 bit data output
430 * EPD_AUO: 0: EINK; 1:AUO
431 * EPD_GDRL: gate scanning direction: 1:button to top 0:top to button
432 * EPD_SDSHR: source scanning direction 1:right to left 0:left to right
433 */
434 tcon_write(tcon, EBC_EPD_CTRL,
435 EINK_MODE_SWAP(1) |
436 DSP_GD_ST(panel->lsl + panel->gdck_sta) |
437 DSP_GD_END(panel->lsl + panel->gdck_sta + panel->lgonl) |
438 DSP_THREE_WIN_MODE(0) |
439 DSP_SDDW_MODE(!!panel->panel_16bit) |
440 EPD_AUO(0) |
441 EPD_GDRL(1) |
442 EPD_SDSHR(1));
443 tcon_write(tcon, EBC_DSP_START,
444 DSP_SDCE_WIDTH(panel->ldl) | SW_BURST_CTRL);
445
446 tcon_write(tcon, EBC_DSP_CTRL,
447 DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) |
448 DSP_VCOM_MODE(1) |
449 DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3));
450
451 tcon_cfg_done(tcon);
452
453 ret = clk_set_rate(&tcon->dclk, panel->sdck * ((panel->panel_16bit ? 7 : 3) + 1));
454 if (ret < 0) {
455 printf("%s: set clock rate failed, %d\n", __func__, ret);
456 return ret;
457 }
458
459 return 0;
460 }
461 #endif
462
ebc_tcon_disable(struct udevice * dev)463 static int ebc_tcon_disable(struct udevice *dev)
464 {
465 return 0;
466 }
467
468 #ifdef CONFIG_ROCKCHIP_RK3568
ebc_tcon_dsp_mode_set(struct udevice * dev,int update_mode,int display_mode,int three_win_mode,int eink_mode)469 static int ebc_tcon_dsp_mode_set(struct udevice *dev, int update_mode,
470 int display_mode, int three_win_mode,
471 int eink_mode)
472 {
473 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
474
475 tcon_update_bits(tcon, EBC_DSP_CTRL,
476 UPDATE_MODE_MASK | DISPLAY_MODE_MASK,
477 DSP_UPDATE_MODE(!!update_mode) |
478 DSP_DISPLAY_MODE(!!display_mode));
479
480 tcon_update_bits(tcon, EBC_EPD_CTRL, THREE_WIN_MODE_MASK,
481 DSP_THREE_WIN_MODE(!!three_win_mode));
482 /* always set frm start bit 0 before real frame start */
483 tcon_update_bits(tcon, EBC_DSP_START,
484 DSP_EINK_MODE_MASK | DSP_FRM_START_MASK,
485 DSP_EINK_MODE(!!eink_mode));
486 tcon_cfg_done(tcon);
487
488 return 0;
489 }
490 #endif
491
ebc_tcon_image_addr_set(struct udevice * dev,u32 pre_image_addr,u32 cur_image_addr)492 static int ebc_tcon_image_addr_set(struct udevice *dev, u32 pre_image_addr,
493 u32 cur_image_addr)
494 {
495 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
496
497 tcon_write(tcon, EBC_WIN_MST0, pre_image_addr);
498 tcon_write(tcon, EBC_WIN_MST1, cur_image_addr);
499 tcon_cfg_done(tcon);
500
501 return 0;
502 }
503
ebc_tcon_frame_addr_set(struct udevice * dev,u32 frame_addr)504 static int ebc_tcon_frame_addr_set(struct udevice *dev, u32 frame_addr)
505 {
506 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
507
508 tcon_write(tcon, EBC_WIN_MST2, frame_addr);
509 tcon_cfg_done(tcon);
510
511 return 0;
512 }
513
ebc_tcon_lut_data_set(struct udevice * dev,unsigned int * lut_data,int frame_count,int lut_32)514 static int ebc_tcon_lut_data_set(struct udevice *dev, unsigned int *lut_data,
515 int frame_count, int lut_32)
516 {
517 int i, lut_size;
518 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
519
520 if ((!lut_32 && frame_count > 256) || (lut_32 && frame_count > 64)) {
521 dev_err(tcon->dev, "frame count over flow\n");
522 return -1;
523 }
524
525 if (lut_32)
526 lut_size = frame_count * 64;
527 else
528 lut_size = frame_count * 16;
529
530 for (i = 0; i < lut_size; i++)
531 tcon_write(tcon, EBC_LUT_DATA_ADDR + (i * 4), lut_data[i]);
532
533 tcon_cfg_done(tcon);
534
535 return 0;
536 }
537
wait_for_last_frame_complete(struct udevice * dev)538 static int wait_for_last_frame_complete(struct udevice *dev)
539 {
540 #ifndef CONFIG_IRQ
541 u32 intr_status;
542 #endif
543 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
544
545 #ifdef CONFIG_IRQ
546 while (1) {
547 if ((last_frame_done == -1) || (last_frame_done == 1))
548 break;
549 msleep(1);
550 }
551 #else
552 /* wait for frame display end*/
553 while (1) {
554 /* first frame don't need to wait*/
555 if (last_frame_done == -1)
556 break;
557 intr_status = readl(tcon->reg + EBC_INT_STATUS);
558 if (intr_status & DSP_END_INT)
559 break;
560 msleep(1);
561 }
562 #endif
563 tcon_update_bits(tcon, EBC_INT_STATUS,
564 DSP_END_INT_CLR, DSP_END_INT_CLR);
565
566 return 0;
567 }
568
569 #ifdef CONFIG_ROCKCHIP_RK3568
ebc_tcon_frame_start(struct udevice * dev,int frame_total)570 static int ebc_tcon_frame_start(struct udevice *dev, int frame_total)
571 {
572 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
573
574 tcon_write(tcon, EBC_INT_STATUS,
575 LINE_FLAG_INT_MASK | DSP_FRM_INT_MASK | FRM_END_INT_MASK);
576 tcon_update_bits(tcon, EBC_DSP_START,
577 DSP_FRM_TOTAL_MASK, DSP_FRM_TOTAL(frame_total - 1));
578 tcon_cfg_done(tcon);
579
580 tcon_update_bits(tcon, EBC_DSP_START,
581 DSP_FRM_START_MASK, DSP_FRM_START);
582 last_frame_done = 0;
583 return 0;
584 }
585 #endif
586
587 #ifdef CONFIG_ROCKCHIP_RK3576
rk3576_ebc_tcon_enable(struct udevice * dev,struct ebc_panel * panel)588 static int rk3576_ebc_tcon_enable(struct udevice *dev, struct ebc_panel *panel)
589 {
590 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
591 u32 width, height, vir_width, vir_height;
592 u32 val;
593 int ret;
594
595 if (panel->rearrange) {
596 width = panel->width * 2;
597 height = panel->height / 2;
598 vir_width = panel->vir_width * 2;
599 vir_height = panel->vir_height / 2;
600 } else {
601 width = panel->width;
602 height = panel->height;
603 vir_width = panel->vir_width;
604 vir_height = panel->vir_height;
605 }
606
607 /* panel timing and win info config */
608 tcon_write(tcon, RK3576_EBC_DSP_HTIMING0,
609 RK3576_DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl + panel->lel) |
610 RK3576_DSP_HS_END(panel->lsl));
611 tcon_write(tcon, RK3576_EBC_DSP_HTIMING1,
612 RK3576_DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) |
613 RK3576_DSP_HACT_ST(panel->lsl + panel->lbl - 1));
614 tcon_write(tcon, RK3576_EBC_DSP_VTIMING0,
615 RK3576_DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl + panel->fel) |
616 RK3576_DSP_VS_END(panel->fsl));
617 tcon_write(tcon, RK3576_EBC_DSP_VTIMING1,
618 RK3576_DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) |
619 RK3576_DSP_VACT_ST(panel->fsl + panel->fbl));
620 tcon_write(tcon, RK3576_EBC_DSP_ACT_INFO,
621 RK3576_DSP_HEIGHT(vir_height) |
622 RK3576_DSP_WIDTH(vir_width));
623 tcon_write(tcon, RK3576_EBC_WIN_VIR,
624 RK3576_WIN_VIR_HEIGHT(height) |
625 RK3576_WIN_VIR_WIDTH(width));
626 tcon_write(tcon, RK3576_EBC_WIN_ACT,
627 RK3576_WIN_ACT_HEIGHT(height) |
628 RK3576_WIN_ACT_WIDTH(width));
629 tcon_write(tcon, RK3576_EBC_WIN_DSP,
630 RK3576_WIN_DSP_HEIGHT(height) |
631 RK3576_WIN_DSP_WIDTH(width));
632 if (width != vir_width || height != vir_height) {
633 if (((vir_width - width) / 2) % 2)
634 dev_warn(dev,
635 "Margin left/right between width/vir_width must be same\n");
636 if (((vir_height - height) / 2) % 2)
637 dev_warn(tcon->dev,
638 "Margin top/bottom between height/vir_height must be same\n");
639
640 val = panel->panel_16bit ? 8 : 4;
641 if (((vir_width - width) / 2) % val)
642 dev_warn(dev,
643 "Margin left/right between width/vir_width must align with %d\n",
644 val);
645
646 val = RK3576_WIN_DSP_YST(panel->fsl + panel->fbl + (vir_height - height) / 2);
647 if (panel->panel_16bit)
648 val |= RK3576_WIN_DSP_XST(panel->lsl + panel->lbl +
649 (vir_width - width) / 2 / 8);
650 else
651 val |= RK3576_WIN_DSP_XST(panel->lsl + panel->lbl +
652 (vir_width - width) / 2 / 4);
653 tcon_write(tcon, RK3576_EBC_WIN_DSP_ST, val);
654 } else {
655 tcon_write(tcon, RK3576_EBC_WIN_DSP_ST,
656 RK3576_WIN_DSP_YST(panel->fsl + panel->fbl) |
657 RK3576_WIN_DSP_XST(panel->lsl + panel->lbl));
658 }
659
660 /*
661 * win2 fifo is 512x64, win fifo is 256x64,
662 * we set fifo almost value (fifo_size - 16(brust_length))
663 *
664 * dma_burst_length mean axi burst length = 16
665 */
666 tcon_write(tcon, RK3576_EBC_WIN_CTRL,
667 RK3576_WIN2_FIFO_ALMOST_FULL_LEVEL(496) |
668 RK3576_DMA_BURST_LENGTH(0) |
669 RK3576_WIN_FIFO_ALMOST_FULL_LEVEL(240) |
670 RK3576_WIN_FMT(Y_DATA_4BPP));
671
672 /* win0 always enable */
673 tcon_write(tcon, RK3576_EBC_WIN0_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) |
674 RK3576_WIN_AXI_GATHER_EN | RK3576_WIN_RID(1) |
675 RK3576_WIN_EN);
676 tcon_write(tcon, RK3576_EBC_WIN1_CTRL, RK3576_WIN_RID(2));
677 tcon_write(tcon, RK3576_EBC_WIN2_CTRL, RK3576_WIN_RID(3));
678
679 /*
680 * RK3576_EBC_EPD_CTRL info:
681 * DSP_GD_END : GCLK falling edge point(SCLK), which count from the rising edge of hsync
682 * DSP_GD_ST: GCLK rising edge point(SCLK), which count from the rising edge of hsync
683 * DSP_THREE_WIN_MODE: 0: lut mode or direct mode; 1: three win mode
684 * DSP_SDDW_MODE: 0: 8 bit data output; 1: 16 bit data output
685 * EPD_AUO: 0: EINK; 1:AUO
686 * EPD_GDRL: gate scanning direction: 1: button to top 0: top to button
687 * EPD_SDSHR: source scanning direction 1: right to left 0: left to right
688 */
689 tcon_write(tcon, RK3576_EBC_EPD_CTRL, RK3576_EINK_MODE_SWAP(1) |
690 RK3576_DSP_GD_ST(panel->lsl + panel->gdck_sta) |
691 RK3576_DSP_GD_END(panel->lsl + panel->gdck_sta + panel->lgonl) |
692 RK3576_DSP_THREE_WIN_MODE(0) |
693 RK3576_DSP_SDDW_MODE(!!panel->panel_16bit) |
694 RK3576_EPD_AUO(0) |
695 RK3576_EPD_GDRL(1) |
696 RK3576_EPD_SDSHR(1));
697
698 tcon_write(tcon, RK3576_EBC_DSP_START, 0);
699
700 if (panel->sdce_width == 0)
701 val = RK3576_DSP_SDCE_WIDTH(panel->ldl);
702 else
703 val = RK3576_DSP_SDCE_WIDTH(panel->sdce_width);
704 tcon_write(tcon, RK3576_EBC_DSP_CTRL2, RK3576_SW_BURST_CTRL | val);
705
706 /**
707 * SDOE_MODE 1 : sdce signal act as vden
708 * SDOE_MODE 0 : sdce signal act as hden
709 */
710 if (panel->sdoe_mode == 1)
711 val = RK3576_DSP_SDOE_MODE(1);
712 else
713 val = RK3576_DSP_SDOE_MODE(0);
714
715 tcon_write(tcon, RK3576_EBC_DSP_CTRL,
716 RK3576_DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) | RK3576_DSP_VCOM_MODE(1) |
717 RK3576_DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3) | val);
718
719 tcon_cfg_done(tcon);
720
721 ret = clk_set_rate(&tcon->dclk,
722 panel->sdck * ((panel->panel_16bit ? 7 : 3) + 1));
723 if (ret < 0) {
724 printf("%s: set clock rate failed, %d\n", __func__, ret);
725 return ret;
726 }
727
728 return 0;
729 }
730
rk3576_ebc_tcon_dsp_mode_set(struct udevice * dev,int update_mode,int display_mode,int three_win_mode,int eink_mode)731 static int rk3576_ebc_tcon_dsp_mode_set(struct udevice *dev, int update_mode,
732 int display_mode, int three_win_mode,
733 int eink_mode)
734 {
735 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
736
737 tcon_write(tcon, RK3576_EBC_WIN1_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) |
738 RK3576_WIN_AXI_GATHER_EN |
739 RK3576_WIN_RID(2) |
740 ((!!display_mode) | (!!three_win_mode)));
741 tcon_write(tcon, RK3576_EBC_WIN2_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) |
742 RK3576_WIN_AXI_GATHER_EN |
743 RK3576_WIN_RID(3) |
744 (!!three_win_mode));
745
746 tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL,
747 RK3576_UPDATE_MODE_MASK | RK3576_DISPLAY_MODE_MASK,
748 RK3576_DSP_UPDATE_MODE(!!update_mode) |
749 RK3576_DSP_DISPLAY_MODE(!!display_mode));
750 tcon_update_bits(tcon, RK3576_EBC_EPD_CTRL, RK3576_THREE_WIN_MODE_MASK,
751 RK3576_DSP_THREE_WIN_MODE(!!three_win_mode));
752 /* always set frm start bit 0 before real frame start */
753 tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL2, RK3576_DSP_EINK_MODE_MASK,
754 RK3576_DSP_EINK_MODE(!!eink_mode));
755 tcon_cfg_done(tcon);
756
757 return 0;
758 }
759
rk3576_ebc_tcon_frame_start(struct udevice * dev,int frame_total)760 static int rk3576_ebc_tcon_frame_start(struct udevice *dev, int frame_total)
761 {
762 struct ebc_tcon_priv *tcon = dev_get_priv(dev);
763
764 tcon_write(tcon, RK3576_EBC_INT_STATUS, RK3576_LINE_FLAG_INT_MASK |
765 RK3576_DSP_FRM_INT_MASK | RK3576_FRM_END_INT_MASK |
766 RK3576_WIN2_EMPTY_INT_MASK | RK3576_WIN1_EMPTY_INT_MASK |
767 RK3576_WIN0_EMPTY_INT_MASK);
768 /* always set frm start bit 0 before real frame start */
769 tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL2, RK3576_DSP_FRM_TOTAL_MASK,
770 RK3576_DSP_FRM_TOTAL(frame_total - 1));
771 tcon_cfg_done(tcon);
772
773 last_frame_done = 0;
774 tcon_write(tcon, RK3576_EBC_DSP_START, 1);
775
776 return 0;
777 }
778 #endif
779
rk_ebc_tcon_probe(struct udevice * dev)780 static int rk_ebc_tcon_probe(struct udevice *dev)
781 {
782 int ret;
783 struct ebc_tcon_priv *priv = dev_get_priv(dev);
784 struct driver *driver = (struct driver *)dev->driver;
785 const struct rk_ebc_tcon_ops *tcon_ops;
786 #ifdef CONFIG_IRQ
787 u32 interrupt[2];
788 int irq;
789 #endif
790
791 tcon_ops = (const struct rk_ebc_tcon_ops *)dev_get_driver_data(dev);
792 driver->ops = tcon_ops;
793
794 priv->dev = dev;
795
796 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
797 ret = clk_set_defaults(dev);
798 if (ret)
799 dev_warn(dev, "clk_set_defaults failed %d\n", ret);
800
801 ret = clk_get_by_name(dev, "dclk", &priv->dclk);
802 if (ret < 0) {
803 printf("%s get clock fail! %d\n", __func__, ret);
804 return -EINVAL;
805 }
806
807 #ifdef CONFIG_IRQ
808 ret = dev_read_u32_array(dev, "interrupts", interrupt, 2);
809 if (ret) {
810 printf("read ebc irq failed:%d\n", ret);
811 return ret;
812 }
813
814 /* convert to Shared Peripheral Interrupt */
815 irq = interrupt[1] + 32;
816 irq_install_handler(irq, ebc_irq_handler, dev);
817 irq_handler_enable(irq);
818 #endif
819 return 0;
820 }
821
822 #ifdef CONFIG_ROCKCHIP_RK3568
823 const struct rk_ebc_tcon_ops rk3568_ebc_tcon_funcs = {
824 .enable = ebc_tcon_enable,
825 .disable = ebc_tcon_disable,
826 .dsp_mode_set = ebc_tcon_dsp_mode_set,
827 .image_addr_set = ebc_tcon_image_addr_set,
828 .frame_addr_set = ebc_tcon_frame_addr_set,
829 .lut_data_set = ebc_tcon_lut_data_set,
830 .frame_start = ebc_tcon_frame_start,
831 .wait_for_last_frame_complete = wait_for_last_frame_complete,
832 };
833 #endif
834
835 #ifdef CONFIG_ROCKCHIP_RK3576
836 const struct rk_ebc_tcon_ops rk3576_ebc_tcon_funcs = {
837 .enable = rk3576_ebc_tcon_enable,
838 .disable = ebc_tcon_disable,
839 .dsp_mode_set = rk3576_ebc_tcon_dsp_mode_set,
840 .image_addr_set = ebc_tcon_image_addr_set,
841 .frame_addr_set = ebc_tcon_frame_addr_set,
842 .lut_data_set = ebc_tcon_lut_data_set,
843 .frame_start = rk3576_ebc_tcon_frame_start,
844 .wait_for_last_frame_complete = wait_for_last_frame_complete,
845 };
846 #endif
847
rk_ebc_tcon_ofdata_to_platdata(struct udevice * dev)848 static int rk_ebc_tcon_ofdata_to_platdata(struct udevice *dev)
849 {
850 fdt_size_t size;
851 fdt_addr_t addr;
852 struct ebc_tcon_priv *priv = dev_get_priv(dev);
853
854 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
855 if (priv->grf <= 0) {
856 debug("%s: Get syscon grf failed (ret=%p)\n",
857 __func__, priv->grf);
858 return -ENXIO;
859 }
860 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
861 if (priv->pmugrf <= 0) {
862 debug("%s: Get syscon pmugrf failed (ret=%p)\n",
863 __func__, priv->grf);
864 return -ENXIO;
865 }
866 addr = dev_read_addr_size(dev, "reg", &size);
867 if (addr == FDT_ADDR_T_NONE) {
868 debug("%s: Get ebc_tcon address failed\n", __func__);
869 return -ENXIO;
870 }
871
872 priv->reg = ioremap(addr, size);
873 priv->reg_len = size;
874 priv->regcache = malloc(size);
875 memset(priv->regcache, 0, size);
876 return 0;
877 }
878
879 static const struct udevice_id ebc_tcon_ids[] = {
880 #ifdef CONFIG_ROCKCHIP_RK3568
881 {
882 .compatible = "rockchip,rk3568-ebc-tcon",
883 .data = (ulong)&rk3568_ebc_tcon_funcs,
884 },
885 #endif
886 #ifdef CONFIG_ROCKCHIP_RK3576
887 {
888 .compatible = "rockchip,rk3576-ebc-tcon",
889 .data = (ulong)&rk3576_ebc_tcon_funcs,
890 },
891 #endif
892 {}
893 };
894
895 U_BOOT_DRIVER(rk_ebc_tcon) = {
896 .name = "rk_ebc_tcon",
897 .id = UCLASS_EBC,
898 .of_match = ebc_tcon_ids,
899 .ofdata_to_platdata = rk_ebc_tcon_ofdata_to_platdata,
900 .probe = rk_ebc_tcon_probe,
901 .priv_auto_alloc_size = sizeof(struct ebc_tcon_priv),
902 };
903
904 UCLASS_DRIVER(ebc_tcon) = {
905 .id = UCLASS_EBC,
906 .name = "ebc_tcon",
907 };
908
909