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Searched refs:duty (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/drivers/pwm/
H A Drk_pwm.c133 unsigned long period, duty; in rk_pwm_set_config_v4() local
137 duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, in rk_pwm_set_config_v4()
141 writel(duty, priv->base + DUTY); in rk_pwm_set_config_v4()
151 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty); in rk_pwm_set_config_v4()
161 unsigned long period, duty; in rk_pwm_set_config_v1() local
185 duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, in rk_pwm_set_config_v1()
189 writel(duty, priv->base + regs->duty); in rk_pwm_set_config_v1()
205 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty); in rk_pwm_set_config_v1()
346 .duty = 0x04,
367 .duty = 0x08,
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H A DKconfig6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
26 programmable period and duty cycle. A 32-bit counter is used.
43 four channels with a programmable period and duty cycle. Only a
44 32KHz clock is supported by the driver but the duty cycle is
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dpwm.h12 unsigned long duty; member
/rk3399_rockchip-uboot/board/siemens/pxm2/
H A Dboard.c339 int duty = PWM_DUTY; in enable_pwm() local
352 writel(duty, &ecap->cap2); in enable_pwm()
353 writel(duty, &ecap->cap4); in enable_pwm()
/rk3399_rockchip-uboot/drivers/power/regulator/
H A DKconfig74 controlled by PWM duty ratio. Some of Rockchip board using this kind
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dstih407-family.dtsi110 max-duty-cycle = <255>;