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Searched refs:data_value (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_a38x.c259 u32 data_value, pipe_enable_mask = 0; in ddr3_tip_a38x_pipe_enable() local
271 (dev_num, PIPE_ENABLE_ADDR, &data_value, MASK_ALL_BITS)); in ddr3_tip_a38x_pipe_enable()
272 data_value = (data_value & (~0xff)) | pipe_enable_mask; in ddr3_tip_a38x_pipe_enable()
273 CHECK_STATUS(ddr3_tip_reg_write(dev_num, PIPE_ENABLE_ADDR, data_value)); in ddr3_tip_a38x_pipe_enable()
286 u32 if_id, u32 reg_addr, u32 data_value, in ddr3_tip_a38x_if_write() argument
295 data_value = (ui_data_read & (~mask)) | (data_value & mask); in ddr3_tip_a38x_if_write()
298 reg_write(reg_addr, data_value); in ddr3_tip_a38x_if_write()
H A Dddr3_training.c184 u32 data_value, enum hws_operation oper_type);
306 u32 data_value = 0, bus_width = 0, page_size = 0, cs_cnt = 0, in hws_ddr3_tip_init_controller() local
379 data_value = in hws_ddr3_tip_init_controller()
388 SDRAM_CONFIGURATION_REG, data_value, in hws_ddr3_tip_init_controller()
430 data_value = 0x7; in hws_ddr3_tip_init_controller()
456 data_value = TIME_2_CLOCK_CYCLES(t_faw, t_ckclk); in hws_ddr3_tip_init_controller()
457 data_value = data_value << 24; in hws_ddr3_tip_init_controller()
460 SDRAM_ACCESS_CONTROL_REG, data_value, in hws_ddr3_tip_init_controller()
463 data_value = in hws_ddr3_tip_init_controller()
511 data_value = in hws_ddr3_tip_init_controller()
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H A Dddr3_training_ip_flow.h291 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
301 u32 reg_addr, u32 data_value, u32 reg_mask);
308 u32 data_value);
H A Dddr3_training_ip_engine.c523 u32 data_value = 0; in ddr3_tip_configure_odpg() local
526 data_value = ((single_pattern << 2) | (tx_phases << 5) | in ddr3_tip_configure_odpg()
531 ODPG_DATA_CONTROL_REG, data_value, 0xaffffffc); in ddr3_tip_configure_odpg()
767 u32 poll_cnt = 0, data_value; in is_odpg_access_done() local
774 data_value = read_data[if_id]; in is_odpg_access_done()
775 if (((data_value >> ODPG_BIST_DONE_BIT_OFFS) & 0x1) == in is_odpg_access_done()
777 data_value = data_value & 0xfffffffe; in is_odpg_access_done()
780 if_id, ODPG_BIST_DONE, data_value, in is_odpg_access_done()
H A Dddr3_debug.c100 u32 if_id, reg_addr, data_value, bus_id; in ddr3_tip_reg_dump() local
131 &data_value)); in ddr3_tip_reg_dump()
132 printf("0x%x ", data_value); in ddr3_tip_reg_dump()
142 &data_value)); in ddr3_tip_reg_dump()
143 printf("0x%x ", data_value); in ddr3_tip_reg_dump()
659 u32 data_value; in read_adll_value() local
677 &data_value)); in read_adll_value()
680 data_value & mask; in read_adll_value()
H A Dddr3_training_pbs.c938 u32 data_value = 0, bit = 0, if_id = 0, pup = 0; in ddr3_tip_print_pbs_result() local
959 &data_value)); in ddr3_tip_print_pbs_result()
960 printf("%d , ", data_value); in ddr3_tip_print_pbs_result()