Searched refs:clk_base (Results 1 – 5 of 5) sorted by relevance
150 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_enable() argument154 data = readl(clk_base); in hi6220_clk_enable()157 writel(bitfield, clk_base); in hi6220_clk_enable()159 data = readl(clk_base + STAT_EN_OFF); in hi6220_clk_enable()166 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_disable() argument170 data = readl(clk_base); in hi6220_clk_disable()173 writel(data, clk_base); in hi6220_clk_disable()175 data = readl(clk_base + STAT_DIS_OFF); in hi6220_clk_disable()
380 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_sys_clk()418 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_ddr_clk()
61 u32 clk_base, clk_mul; in atmel_sdhci_probe() local82 clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; in atmel_sdhci_probe()85 gck_rate = clk_base * 1000000 * (clk_mul + 1); in atmel_sdhci_probe()
578 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_sys_clk()615 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_ddr_clk()
81 u8 clk_base[2]; /* Clock Frequency Base Reg */ member