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Searched refs:XCHAL_ICACHE_LINEWIDTH (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/xtensa/include/asm/
H A Dcacheasm.h19 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
94 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
132 XCHAL_ICACHE_LINEWIDTH
169 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
206 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h122 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h141 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h189 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro