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Searched refs:XCHAL_DCACHE_LINEWIDTH (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/xtensa/include/asm/
H A Dcacheasm.h18 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
85 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
103 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
112 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
122 XCHAL_DCACHE_LINEWIDTH
142 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
151 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
160 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
179 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
188 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
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/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h123 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h142 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h190 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro