Searched refs:WL (Results 1 – 3 of 3) sorted by relevance
43 writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2); in ddr2_phy_init()152 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()154 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()169 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()197 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
20 #define WL 4 macro
84 reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */