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Searched refs:SYSCLK (Results 1 – 22 of 22) sorted by relevance

/rk3399_rockchip-uboot/doc/
H A DREADME.mpc85xxcds150 XXXX1000 == CCB:SYSCLK 8:1
151 XXXX1010 == CCB:SYSCLK 10:1
184 XXXX0000 == CCB:SYSCLK 16:1
186 XXXX0010 == CCB:SYSCLK 2:1
187 XXXX0011 == CCB:SYSCLK 3:1
188 XXXX0100 == CCB:SYSCLK 4:1
189 XXXX0101 == CCB:SYSCLK 5:1
190 XXXX0110 == CCB:SYSCLK 6:1
192 XXXX1000 == CCB:SYSCLK 8:1
193 XXXX1001 == CCB:SYSCLK 9:1
[all …]
H A DREADME.b4860qds91 - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and
/rk3399_rockchip-uboot/board/freescale/mpc8610hpcd/
H A DREADME50 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
51 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
65 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Dmicrochip,clock.h15 #define SYSCLK 3 macro
/rk3399_rockchip-uboot/board/freescale/mpc8641hpcn/
H A DREADME30 SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
31 001 :: SYSCLK = 40MHz
167 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
168 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
182 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/rk3399_rockchip-uboot/board/freescale/mpc8544ds/
H A DREADME68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/rk3399_rockchip-uboot/board/freescale/mpc8572ds/
H A DREADME62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A DREADME75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
/rk3399_rockchip-uboot/board/freescale/t4qds/
H A DREADME54 Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
58 System and DDR clock (SYSCLK, “DDRCLK”)
/rk3399_rockchip-uboot/board/sbc8548/
H A DREADME37 to reflect a different CCB:SYSCLK ratio]
246 D15 SYSCLK 66MHz 33MHz
/rk3399_rockchip-uboot/board/freescale/ls1021aqds/
H A DREADME89 - System and DDR clock (SYSCLK, DDRCLK)
/rk3399_rockchip-uboot/board/freescale/ls1021atwr/
H A DREADME88 - System and DDR clock (SYSCLK, DDRCLK)
/rk3399_rockchip-uboot/board/freescale/t104xrdb/
H A DREADME115 - System and DDR clock (SYSCLK, “DDRCLK”)
147 - System and DDR clock (SYSCLK, “DDRCLK”)
/rk3399_rockchip-uboot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h260 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
261 DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
/rk3399_rockchip-uboot/board/freescale/t102xqds/
H A DREADME109 - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
113 - System and DDR clock (SYSCLK, DDRCLK).
/rk3399_rockchip-uboot/board/freescale/t1040qds/
H A DREADME74 - System and DDR clock (SYSCLK, “DDRCLK”)
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra114/
H A Dpinmux.c231 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
/rk3399_rockchip-uboot/board/nvidia/dalmore/
H A Dpinmux-config-dalmore.h221 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/
H A Dpinmux.c226 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
/rk3399_rockchip-uboot/board/toradex/colibri_t30/
H A Dpinmux-config-colibri_t30.h256 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/rk3399_rockchip-uboot/board/nvidia/cardhu/
H A Dpinmux-config-cardhu.h248 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/rk3399_rockchip-uboot/board/toradex/apalis_t30/
H A Dpinmux-config-apalis_t30.h266 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),