Searched refs:SCLK (Results 1 – 7 of 7) sorted by relevance
| /rk3399_rockchip-uboot/board/renesas/stout/ |
| H A D | cpld.c | 16 #define SCLK GPIO_GP_3_24 macro
35 gpio_set_value(SCLK, 1); in cpld_read()
37 gpio_set_value(SCLK, 0); in cpld_read()
42 gpio_set_value(SCLK, 1); in cpld_read()
43 gpio_set_value(SCLK, 0); in cpld_read()
47 gpio_set_value(SCLK, 1); in cpld_read()
50 gpio_set_value(SCLK, 0); in cpld_read()
62 gpio_set_value(SCLK, 1); in cpld_write()
64 gpio_set_value(SCLK, 0); in cpld_write()
69 gpio_set_value(SCLK, 1); in cpld_write()
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| /rk3399_rockchip-uboot/board/renesas/ulcb/ |
| H A D | cpld.c | 15 #define SCLK GPIO_GP_6_8 macro
51 gpio_set_value(SCLK, set); in ulcb_softspi_scl()
63 gpio_set_value(SCLK, 1); in cpld_rw()
64 gpio_set_value(SCLK, 0); in cpld_rw()
100 gpio_request(SCLK, NULL); in cpld_init()
105 gpio_direction_output(SCLK, 0); in cpld_init()
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| /rk3399_rockchip-uboot/drivers/rtc/ |
| H A D | ds1302.c | 16 #define SCLK 0x400 macro
20 #define RESET rtc_go_low(RST), rtc_go_low(SCLK)
21 #define N_RESET rtc_go_high(RST), rtc_go_low(SCLK)
23 #define CLOCK_HIGH rtc_go_high(SCLK)
24 #define CLOCK_LOW rtc_go_low(SCLK)
200 rtc_go_output(DATA|SCLK|RST); in rtc_init()
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| /rk3399_rockchip-uboot/include/ |
| H A D | sym53c8xx.h | 188 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | armada-385-turris-omnia.dts | 377 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | Kconfig | 362 string "SPI SCLK pin for LCD related config job"
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| /rk3399_rockchip-uboot/ |
| H A D | README | 2013 the i2c SCLK line directly, either by using the
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