1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Chen Shunqing <csq@rock-chips.com>
6 */
7
8 #ifndef HDMITX_H
9 #define HDMITX_H
10
11 #include "rk628.h"
12
13 #define HDMI_BASE 0x70000
14 #define HDMI_REG_STRIDE 4
15 #define HDMITX_REG(x) ((x * HDMI_REG_STRIDE) + HDMI_BASE)
16
17 #define DDC_SEGMENT_ADDR 0x30
18
19 enum PWR_MODE {
20 NORMAL,
21 LOWER_PWR,
22 };
23
24 #define HDMI_SCL_RATE (100 * 1000)
25 #define DDC_BUS_FREQ_L HDMITX_REG(0x4b)
26 #define DDC_BUS_FREQ_H HDMITX_REG(0x4c)
27
28 #define HDMI_SYS_CTRL HDMITX_REG(0x00)
29 #define RST_ANALOG_MASK BIT(6)
30 #define NOT_RST_ANALOG(x) UPDATE(x, 6, 6)
31 #define RST_DIGITAL_MASK BIT(5)
32 #define NOT_RST_DIGITAL(x) UPDATE(x, 5, 5)
33 #define REG_CLK_INV_MASK BIT(4)
34 #define REG_CLK_INV(x) UPDATE(x, 4, 4)
35 #define VCLK_INV_MASK BIT(3)
36 #define VCLK_INV(x) UPDATE(x, 3, 3)
37 #define REG_CLK_SOURCE_MASK BIT(2)
38 #define REG_CLK_SOURCE(x) UPDATE(x, 2, 2)
39 #define POWER_MASK BIT(1)
40 #define PWR_OFF(x) UPDATE(x, 1, 1)
41 #define INT_POL_MASK BIT(0)
42 #define INT_POL(x) UPDATE(x, 0, 0)
43
44 #define HDMI_VIDEO_CONTROL1 HDMITX_REG(0x01)
45 #define VIDEO_INPUT_FORMAT_MASK GENMASK(3, 1)
46 #define VIDEO_INPUT_SDR_RGB444 UPDATE(0x0, 3, 1)
47 #define VIDEO_INPUT_DDR_RGB444 UPDATE(0x5, 3, 1)
48 #define VIDEO_INPUT_DDR_YCBCR422 UPDATE(0x6, 3, 1)
49 #define DE_SOURCE_MASK BIT(0)
50 #define DE_SOURCE(x) UPDATE(x, 0, 0)
51
52 #define HDMI_VIDEO_CONTROL2 HDMITX_REG(0x02)
53 #define VIDEO_OUTPUT_COLOR_MASK GENMASK(7, 6)
54 #define VIDEO_OUTPUT_RRGB444 UPDATE(0x0, 7, 6)
55 #define VIDEO_OUTPUT_YCBCR444 UPDATE(0x1, 7, 6)
56 #define VIDEO_OUTPUT_YCBCR422 UPDATE(0x2, 7, 6)
57 #define VIDEO_INPUT_BITS_MASK GENMASK(5, 4)
58 #define VIDEO_INPUT_12BITS UPDATE(0x0, 5, 4)
59 #define VIDEO_INPUT_10BITS UPDATE(0x1, 5, 4)
60 #define VIDEO_INPUT_REVERT UPDATE(0x2, 5, 4)
61 #define VIDEO_INPUT_8BITS UPDATE(0x3, 5, 4)
62 #define VIDEO_INPUT_CSP_MASK BIT(1)
63 #define VIDEO_INPUT_CSP(x) UPDATE(x, 0, 0)
64
65 #define HDMI_VIDEO_CONTROL HDMITX_REG(0x03)
66 #define VIDEO_AUTO_CSC_MASK BIT(7)
67 #define VIDEO_AUTO_CSC(x) UPDATE(x, 7, 7)
68 #define VIDEO_C0_C2_SWAP_MASK BIT(0)
69 #define VIDEO_C0_C2_SWAP(x) UPDATE(x, 0, 0)
70 enum {
71 C0_C2_CHANGE_ENABLE = 0,
72 C0_C2_CHANGE_DISABLE = 1,
73 AUTO_CSC_DISABLE = 0,
74 AUTO_CSC_ENABLE = 1,
75 };
76
77 #define HDMI_VIDEO_CONTROL3 HDMITX_REG(0x04)
78 #define COLOR_DEPTH_NOT_INDICATED_MASK BIT(4)
79 #define COLOR_DEPTH_NOT_INDICATED(x) UPDATE(x, 4, 4)
80 #define SOF_MASK BIT(3)
81 #define SOF_DISABLE(x) UPDATE(x, 3, 3)
82 #define CSC_MASK BIT(0)
83 #define CSC_ENABLE(x) UPDATE(x, 0, 0)
84
85 #define HDMI_AV_MUTE HDMITX_REG(0x05)
86 #define AVMUTE_CLEAR_MASK BIT(7)
87 #define AVMUTE_CLEAR(x) UPDATE(x, 7, 7)
88 #define AVMUTE_ENABLE_MASK BIT(6)
89 #define AVMUTE_ENABLE(x) UPDATE(x, 6, 6)
90 #define AUDIO_PD_MASK BIT(2)
91 #define AUDIO_PD(x) UPDATE(x, 2, 2)
92 #define AUDIO_MUTE_MASK BIT(1)
93 #define AUDIO_MUTE(x) UPDATE(x, 1, 1)
94 #define VIDEO_BLACK_MASK BIT(0)
95 #define VIDEO_MUTE(x) UPDATE(x, 0, 0)
96
97 #define HDMI_VIDEO_TIMING_CTL HDMITX_REG(0x08)
98 #define HSYNC_POLARITY(x) UPDATE(x, 3, 3)
99 #define VSYNC_POLARITY(x) UPDATE(x, 2, 2)
100 #define INETLACE(x) UPDATE(x, 1, 1)
101 #define EXTERANL_VIDEO(x) UPDATE(x, 0, 0)
102
103 #define HDMI_VIDEO_EXT_HTOTAL_L HDMITX_REG(0x09)
104 #define HDMI_VIDEO_EXT_HTOTAL_H HDMITX_REG(0x0a)
105 #define HDMI_VIDEO_EXT_HBLANK_L HDMITX_REG(0x0b)
106 #define HDMI_VIDEO_EXT_HBLANK_H HDMITX_REG(0x0c)
107 #define HDMI_VIDEO_EXT_HDELAY_L HDMITX_REG(0x0d)
108 #define HDMI_VIDEO_EXT_HDELAY_H HDMITX_REG(0x0e)
109 #define HDMI_VIDEO_EXT_HDURATION_L HDMITX_REG(0x0f)
110 #define HDMI_VIDEO_EXT_HDURATION_H HDMITX_REG(0x10)
111 #define HDMI_VIDEO_EXT_VTOTAL_L HDMITX_REG(0x11)
112 #define HDMI_VIDEO_EXT_VTOTAL_H HDMITX_REG(0x12)
113 #define HDMI_VIDEO_EXT_VBLANK HDMITX_REG(0x13)
114 #define HDMI_VIDEO_EXT_VDELAY HDMITX_REG(0x14)
115 #define HDMI_VIDEO_EXT_VDURATION HDMITX_REG(0x15)
116
117 #define HDMI_VIDEO_CSC_COEF HDMITX_REG(0x18)
118
119 #define HDMI_AUDIO_CTRL1 HDMITX_REG(0x35)
120 enum {
121 CTS_SOURCE_INTERNAL = 0,
122 CTS_SOURCE_EXTERNAL = 1,
123 };
124
125 #define CTS_SOURCE(x) UPDATE(x, 7, 7)
126
127 enum {
128 DOWNSAMPLE_DISABLE = 0,
129 DOWNSAMPLE_1_2 = 1,
130 DOWNSAMPLE_1_4 = 2,
131 };
132
133 #define DOWN_SAMPLE(x) UPDATE(x, 6, 5)
134
135 enum {
136 AUDIO_SOURCE_IIS = 0,
137 AUDIO_SOURCE_SPDIF = 1,
138 };
139
140 #define AUDIO_SOURCE(x) UPDATE(x, 4, 3)
141 #define MCLK_ENABLE(x) UPDATE(x, 2, 2)
142
143 enum {
144 MCLK_128FS = 0,
145 MCLK_256FS = 1,
146 MCLK_384FS = 2,
147 MCLK_512FS = 3,
148 };
149
150 #define MCLK_RATIO(x) UPDATE(x, 1, 0)
151
152 #define AUDIO_SAMPLE_RATE HDMITX_REG(0x37)
153 enum {
154 AUDIO_32K = 0x3,
155 AUDIO_441K = 0x0,
156 AUDIO_48K = 0x2,
157 AUDIO_882K = 0x8,
158 AUDIO_96K = 0xa,
159 AUDIO_1764K = 0xc,
160 AUDIO_192K = 0xe,
161 };
162
163 #define AUDIO_I2S_MODE HDMITX_REG(0x38)
164 enum {
165 I2S_CHANNEL_1_2 = 1,
166 I2S_CHANNEL_3_4 = 3,
167 I2S_CHANNEL_5_6 = 7,
168 I2S_CHANNEL_7_8 = 0xf
169 };
170
171 #define I2S_CHANNEL(x) UPDATE(x, 5, 2)
172
173 enum {
174 I2S_STANDARD = 0,
175 I2S_LEFT_JUSTIFIED = 1,
176 I2S_RIGHT_JUSTIFIED = 2,
177 };
178
179 #define I2S_MODE(x) UPDATE(x, 1, 0)
180
181 #define AUDIO_I2S_MAP HDMITX_REG(0x39)
182 #define AUDIO_I2S_SWAPS_SPDIF HDMITX_REG(0x3a)
183 #define N_32K 0x1000
184 #define N_441K 0x1880
185 #define N_882K 0x3100
186 #define N_1764K 0x6200
187 #define N_48K 0x1800
188 #define N_96K 0x3000
189 #define N_192K 0x6000
190
191 #define HDMI_AUDIO_CHANNEL_STATUS HDMITX_REG(0x3e)
192 #define AUDIO_STATUS_NLPCM_MASK BIT(7)
193 #define AUDIO_STATUS_NLPCM(x) UPDATE(x, 7, 7)
194 #define AUDIO_STATUS_USE_MASK BIT(6)
195 #define AUDIO_STATUS_COPYRIGHT_MASK BIT(5)
196 #define AUDIO_STATUS_ADDITION_MASK GENMASK(3, 2)
197 #define AUDIO_STATUS_CLK_ACCURACY_MASK GENMASK(1, 1)
198
199 #define AUDIO_N_H HDMITX_REG(0x3f)
200 #define AUDIO_N_M HDMITX_REG(0x40)
201 #define AUDIO_N_L HDMITX_REG(0x41)
202
203 #define HDMI_AUDIO_CTS_H HDMITX_REG(0x45)
204 #define HDMI_AUDIO_CTS_M HDMITX_REG(0x46)
205 #define HDMI_AUDIO_CTS_L HDMITX_REG(0x47)
206
207 #define HDMI_DDC_CLK_L HDMITX_REG(0x4b)
208 #define HDMI_DDC_CLK_H HDMITX_REG(0x4c)
209
210 #define HDMI_EDID_SEGMENT_POINTER HDMITX_REG(0x4d)
211 #define HDMI_EDID_WORD_ADDR HDMITX_REG(0x4e)
212 #define HDMI_EDID_FIFO_OFFSET HDMITX_REG(0x4f)
213 #define HDMI_EDID_FIFO_ADDR HDMITX_REG(0x50)
214
215 #define HDMI_PACKET_SEND_MANUAL HDMITX_REG(0x9c)
216 #define HDMI_PACKET_SEND_AUTO HDMITX_REG(0x9d)
217 #define PACKET_GCP_EN_MASK BIT(7)
218 #define PACKET_GCP_EN(x) UPDATE(x, 7, 7)
219 #define PACKET_MSI_EN_MASK BIT(6)
220 #define PACKET_MSI_EN(x) UPDATE(x, 6, 6)
221 #define PACKET_SDI_EN_MASK BIT(5)
222 #define PACKET_SDI_EN(x) UPDATE(x, 5, 5)
223 #define PACKET_VSI_EN_MASK BIT(4)
224 #define PACKET_VSI_EN(x) UPDATE(x, 4, 4)
225
226 #define HDMI_CONTROL_PACKET_BUF_INDEX HDMITX_REG(0x9f)
227 enum {
228 INFOFRAME_VSI = 0x05,
229 INFOFRAME_AVI = 0x06,
230 INFOFRAME_AAI = 0x08,
231 };
232
233 #define HDMI_CONTROL_PACKET_ADDR HDMITX_REG(0xa0)
234 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
235 enum {
236 AVI_COLOR_MODE_RGB = 0,
237 AVI_COLOR_MODE_YCBCR422 = 1,
238 AVI_COLOR_MODE_YCBCR444 = 2,
239 AVI_COLORIMETRY_NO_DATA = 0,
240
241 AVI_COLORIMETRY_SMPTE_170M = 1,
242 AVI_COLORIMETRY_ITU709 = 2,
243 AVI_COLORIMETRY_EXTENDED = 3,
244
245 AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
246 AVI_CODED_FRAME_ASPECT_4_3 = 1,
247 AVI_CODED_FRAME_ASPECT_16_9 = 2,
248
249 ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
250 ACTIVE_ASPECT_RATE_4_3 = 0x09,
251 ACTIVE_ASPECT_RATE_16_9 = 0x0A,
252 ACTIVE_ASPECT_RATE_14_9 = 0x0B,
253 };
254
255 #define HDMI_HDCP_CTRL HDMITX_REG(0x52)
256 #define HDMI_DVI_MASK BIT(1)
257 #define HDMI_DVI(x) UPDATE(x, 1, 1)
258
259 #define HDMI_INTERRUPT_MASK1 HDMITX_REG(0xc0)
260 #define INT_EDID_READY_MASK BIT(2)
261 #define HDMI_INTERRUPT_STATUS1 HDMITX_REG(0xc1)
262 #define INT_ACTIVE_VSYNC_MASK BIT(5)
263 #define INT_EDID_READY BIT(2)
264
265 #define HDMI_INTERRUPT_MASK2 HDMITX_REG(0xc2)
266 #define HDMI_INTERRUPT_STATUS2 HDMITX_REG(0xc3)
267 #define INT_HDCP_ERR BIT(7)
268 #define INT_BKSV_FLAG BIT(6)
269 #define INT_HDCP_OK BIT(4)
270
271 #define HDMI_STATUS HDMITX_REG(0xc8)
272 #define HOTPLUG_STATUS BIT(7)
273 #define MASK_INT_HOTPLUG_MASK BIT(5)
274 #define MASK_INT_HOTPLUG(x) UPDATE(x, 5, 5)
275 #define INT_HOTPLUG BIT(1)
276
277 #define HDMI_COLORBAR HDMITX_REG(0xc9)
278
279 #define HDMI_PHY_SYNC HDMITX_REG(0xce)
280 #define HDMI_PHY_SYS_CTL HDMITX_REG(0xe0)
281 #define TMDS_CLK_SOURCE_MASK BIT(5)
282 #define TMDS_CLK_SOURCE(x) UPDATE(x, 5, 5)
283 #define PHASE_CLK_MASK BIT(4)
284 #define PHASE_CLK(x) UPDATE(x, 4, 4)
285 #define TMDS_PHASE_SEL_MASK BIT(3)
286 #define TMDS_PHASE_SEL(x) UPDATE(x, 3, 3)
287 #define BANDGAP_PWR_MASK BIT(2)
288 #define BANDGAP_PWR(x) UPDATE(x, 2, 2)
289 #define PLL_PWR_DOWN_MASK BIT(1)
290 #define PLL_PWR_DOWN(x) UPDATE(x, 1, 1)
291 #define TMDS_CHG_PWR_DOWN_MASK BIT(0)
292 #define TMDS_CHG_PWR_DOWN(x) UPDATE(x, 0, 0)
293
294 #define HDMI_PHY_CHG_PWR HDMITX_REG(0xe1)
295 #define CLK_CHG_PWR(x) UPDATE(x, 3, 3)
296 #define DATA_CHG_PWR(x) UPDATE(x, 2, 0)
297
298 #define HDMI_PHY_DRIVER HDMITX_REG(0xe2)
299 #define CLK_MAIN_DRIVER(x) UPDATE(x, 7, 4)
300 #define DATA_MAIN_DRIVER(x) UPDATE(x, 3, 0)
301
302 #define HDMI_PHY_PRE_EMPHASIS HDMITX_REG(0xe3)
303 #define PRE_EMPHASIS(x) UPDATE(x, 6, 4)
304 #define CLK_PRE_DRIVER(x) UPDATE(x, 3, 2)
305 #define DATA_PRE_DRIVER(x) UPDATE(x, 1, 0)
306
307 #define PHY_FEEDBACK_DIV_RATIO_LOW HDMITX_REG(0xe7)
308 #define FEEDBACK_DIV_LOW(x) UPDATE(x, 7, 0)
309 #define PHY_FEEDBACK_DIV_RATIO_HIGH HDMITX_REG(0xe8)
310 #define FEEDBACK_DIV_HIGH(x) UPDATE(x, 0, 0)
311
312 #define HDMI_PHY_PRE_DIV_RATIO HDMITX_REG(0xed)
313 #define PRE_DIV_RATIO(x) UPDATE(x, 4, 0)
314
315 #define HDMI_CEC_CTRL HDMITX_REG(0xd0)
316 #define ADJUST_FOR_HISENSE_MASK BIT(6)
317 #define REJECT_RX_BROADCAST_MASK BIT(5)
318 #define BUSFREETIME_ENABLE_MASK BIT(2)
319 #define REJECT_RX_MASK BIT(1)
320 #define START_TX_MASK BIT(0)
321
322 #define HDMI_CEC_DATA HDMITX_REG(0xd1)
323 #define HDMI_CEC_TX_OFFSET HDMITX_REG(0xd2)
324 #define HDMI_CEC_RX_OFFSET HDMITX_REG(0xd3)
325 #define HDMI_CEC_CLK_H HDMITX_REG(0xd4)
326 #define HDMI_CEC_CLK_L HDMITX_REG(0xd5)
327 #define HDMI_CEC_TX_LENGTH HDMITX_REG(0xd6)
328 #define HDMI_CEC_RX_LENGTH HDMITX_REG(0xd7)
329 #define HDMI_CEC_TX_INT_MASK HDMITX_REG(0xd8)
330 #define TX_DONE_MASK BIT(3)
331 #define TX_NOACK_MASK BIT(2)
332 #define TX_BROADCAST_REJ_MASK BIT(1)
333 #define TX_BUSNOTFREE_MASK BIT(0)
334
335 #define HDMI_CEC_RX_INT_MASK HDMITX_REG(0xd9)
336 #define RX_LA_ERR_MASK BIT(4)
337 #define RX_GLITCH_MASK BIT(3)
338 #define RX_DONE_MASK BIT(0)
339
340 #define HDMI_CEC_TX_INT HDMITX_REG(0xda)
341 #define HDMI_CEC_RX_INT HDMITX_REG(0xdb)
342 #define HDMI_CEC_BUSFREETIME_L HDMITX_REG(0xdc)
343 #define HDMI_CEC_BUSFREETIME_H HDMITX_REG(0xdd)
344 #define HDMI_CEC_LOGICADDR HDMITX_REG(0xde)
345 #define HDMI_COLOR_BAR HDMITX_REG(0xc9)
346 #define VIDEO_BIST_MODE_MASK GENMASK(7, 6)
347 #define VIDEO_BIST_MODE(x) UPDATE(x, 7, 6)
348 #define DISABLE_COLORBAR_BIST_MASK BIT(4)
349 #define DISABLE_COLORBAR_BIST(x) UPDATE(x, 4, 4)
350 #define HDMI_MAX_REG HDMITX_REG(0xed)
351
352 #ifdef CONFIG_RK628_MISC_HDMITX
353 void rk628_hdmitx_disable(struct rk628 *rk628);
354 int rk628_hdmitx_enable(struct rk628 *rk628);
355 void rk628_hdmitx_create_debugfs_file(struct rk628 *rk628);
356 #else
rk628_hdmitx_disable(struct rk628 * rk628)357 static inline void rk628_hdmitx_disable(struct rk628 *rk628)
358 {
359 }
360
rk628_hdmitx_enable(struct rk628 * rk628)361 static inline int rk628_hdmitx_enable(struct rk628 *rk628)
362 {
363 return 0;
364 }
365
rk628_hdmitx_create_debugfs_file(struct rk628 * rk628)366 static inline void rk628_hdmitx_create_debugfs_file(struct rk628 *rk628)
367 {
368 }
369 #endif
370
371 #endif
372