1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2024 Rockchip Electronics Co., Ltd
4 *
5 * Author: Guochun Huang <hero.huang@rock-chips.com>
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <dm/device-internal.h>
11 #include <asm/unaligned.h>
12 #include <linux/math64.h>
13
14 #include "rk628.h"
15 #include "rk628_dsi.h"
16 #include "rk628_combtxphy.h"
17 #include "rk628_cru.h"
18 #include "panel.h"
19
20
21 /* Test Code: 0x44 (HS RX Control of Lane 0) */
22 #define HSFREQRANGE(x) UPDATE(x, 6, 1)
23
24 /* request ACK from peripheral */
25 #define RK628_MIPI_DSI_MSG_REQ_ACK BIT(0)
26 /* use Low Power Mode to transmit message */
27 #define RK628_MIPI_DSI_MSG_USE_LPM BIT(1)
28
29 enum rk628_dsi_vid_mode_type {
30 RK628_DSI_VIDEO_MODE,
31 RK628_DSI_COMMAND_MODE,
32 };
33
34 enum dpi_color_coding {
35 DPI_COLOR_CODING_16BIT_1,
36 DPI_COLOR_CODING_16BIT_2,
37 DPI_COLOR_CODING_16BIT_3,
38 DPI_COLOR_CODING_18BIT_1,
39 DPI_COLOR_CODING_18BIT_2,
40 DPI_COLOR_CODING_24BIT,
41 };
42
43 enum {
44 VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
45 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
46 VID_MODE_TYPE_BURST,
47 };
48
49 /* MIPI DSI Processor-to-Peripheral transaction types */
50 enum {
51 RK628_MIPI_DSI_V_SYNC_START = 0x01,
52 RK628_MIPI_DSI_V_SYNC_END = 0x11,
53 RK628_MIPI_DSI_H_SYNC_START = 0x21,
54 RK628_MIPI_DSI_H_SYNC_END = 0x31,
55
56 RK628_MIPI_DSI_COLOR_MODE_OFF = 0x02,
57 RK628_MIPI_DSI_COLOR_MODE_ON = 0x12,
58 RK628_MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
59 RK628_MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
60
61 RK628_MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
62 RK628_MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
63 RK628_MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
64
65 RK628_MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
66 RK628_MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
67 RK628_MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
68
69 RK628_MIPI_DSI_DCS_SHORT_WRITE = 0x05,
70 RK628_MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
71
72 RK628_MIPI_DSI_DCS_READ = 0x06,
73
74 RK628_MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
75 RK628_MIPI_DSI_PPS_LONG_WRITE = 0x0A,
76
77 RK628_MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
78
79 RK628_MIPI_DSI_END_OF_TRANSMISSION = 0x08,
80
81 RK628_MIPI_DSI_NULL_PACKET = 0x09,
82 RK628_MIPI_DSI_BLANKING_PACKET = 0x19,
83 RK628_MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
84 RK628_MIPI_DSI_DCS_LONG_WRITE = 0x39,
85
86 RK628_MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
87 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
88 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
89
90 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
91 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
92 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
93
94 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
95 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
96 RK628_MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
97 RK628_MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
98 };
99
100 /* MIPI DSI Peripheral-to-Processor transaction types */
101 enum {
102 RK628_MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
103 RK628_MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
104 RK628_MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
105 RK628_MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
106 RK628_MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
107 RK628_MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
108 RK628_MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
109 RK628_MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
110 };
111
112 /* MIPI DCS commands */
113 enum {
114 RK628_MIPI_DCS_NOP = 0x00,
115 RK628_MIPI_DCS_SOFT_RESET = 0x01,
116 RK628_MIPI_DCS_GET_DISPLAY_ID = 0x04,
117 RK628_MIPI_DCS_GET_RED_CHANNEL = 0x06,
118 RK628_MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
119 RK628_MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
120 RK628_MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
121 RK628_MIPI_DCS_GET_POWER_MODE = 0x0A,
122 RK628_MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
123 RK628_MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
124 RK628_MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
125 RK628_MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
126 RK628_MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
127 RK628_MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
128 RK628_MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
129 RK628_MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
130 RK628_MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
131 RK628_MIPI_DCS_EXIT_INVERT_MODE = 0x20,
132 RK628_MIPI_DCS_ENTER_INVERT_MODE = 0x21,
133 RK628_MIPI_DCS_SET_GAMMA_CURVE = 0x26,
134 RK628_MIPI_DCS_SET_DISPLAY_OFF = 0x28,
135 RK628_MIPI_DCS_SET_DISPLAY_ON = 0x29,
136 RK628_MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
137 RK628_MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
138 RK628_MIPI_DCS_WRITE_MEMORY_START = 0x2C,
139 RK628_MIPI_DCS_WRITE_LUT = 0x2D,
140 RK628_MIPI_DCS_READ_MEMORY_START = 0x2E,
141 RK628_MIPI_DCS_SET_PARTIAL_AREA = 0x30,
142 RK628_MIPI_DCS_SET_SCROLL_AREA = 0x33,
143 RK628_MIPI_DCS_SET_TEAR_OFF = 0x34,
144 RK628_MIPI_DCS_SET_TEAR_ON = 0x35,
145 RK628_MIPI_DCS_SET_ADDRESS_MODE = 0x36,
146 RK628_MIPI_DCS_SET_SCROLL_START = 0x37,
147 RK628_MIPI_DCS_EXIT_IDLE_MODE = 0x38,
148 RK628_MIPI_DCS_ENTER_IDLE_MODE = 0x39,
149 RK628_MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
150 RK628_MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
151 RK628_MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
152 RK628_MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
153 RK628_MIPI_DCS_GET_SCANLINE = 0x45,
154 RK628_MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
155 RK628_MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */
156 RK628_MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */
157 RK628_MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */
158 RK628_MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */
159 RK628_MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */
160 RK628_MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
161 RK628_MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
162 RK628_MIPI_DCS_READ_DDB_START = 0xA1,
163 RK628_MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
164 };
165
166 /**
167 * struct rk628_mipi_dsi_msg - read/write DSI buffer
168 * @channel: virtual channel id
169 * @type: payload data type
170 * @flags: flags controlling this message transmission
171 * @tx_len: length of @tx_buf
172 * @tx_buf: data to be written
173 * @rx_len: length of @rx_buf
174 * @rx_buf: data to be read, or NULL
175 */
176 struct rk628_mipi_dsi_msg {
177 u8 channel;
178 u8 type;
179 u16 flags;
180
181 size_t tx_len;
182 const void *tx_buf;
183
184 size_t rx_len;
185 void *rx_buf;
186 };
187
188 /**
189 * struct rk628_mipi_dsi_packet - represents a MIPI DSI packet in protocol format
190 * @size: size (in bytes) of the packet
191 * @header: the four bytes that make up the header (Data ID, Word Count or
192 * Packet Data, and ECC)
193 * @payload_length: number of bytes in the payload
194 * @payload: a pointer to a buffer containing the payload, if any
195 */
196 struct rk628_mipi_dsi_packet {
197 size_t size;
198 u8 header[4];
199 size_t payload_length;
200 const u8 *payload;
201 };
202
dsi_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u32 reg,u32 val)203 static inline int dsi_write(struct rk628 *rk628, const struct rk628_dsi *dsi,
204 u32 reg, u32 val)
205 {
206 unsigned int dsi_base;
207
208 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
209
210 return rk628_i2c_write(rk628, dsi_base + reg, val);
211 }
212
dsi_read(struct rk628 * rk628,const struct rk628_dsi * dsi,u32 reg,u32 * val)213 static inline int dsi_read(struct rk628 *rk628, const struct rk628_dsi *dsi,
214 u32 reg, u32 *val)
215 {
216 unsigned int dsi_base;
217
218 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
219
220 return rk628_i2c_read(rk628, dsi_base + reg, val);
221 }
222
dsi_update_bits(struct rk628 * rk628,const struct rk628_dsi * dsi,u32 reg,u32 mask,u32 val)223 static inline int dsi_update_bits(struct rk628 *rk628,
224 const struct rk628_dsi *dsi,
225 u32 reg, u32 mask, u32 val)
226 {
227 unsigned int dsi_base;
228
229 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
230
231 return rk628_i2c_update_bits(rk628, dsi_base + reg, mask, val);
232 }
233
rk628_dsi_parse(struct rk628 * rk628,ofnode dsi_np)234 int rk628_dsi_parse(struct rk628 *rk628, ofnode dsi_np)
235 {
236 const char *string;
237 int ret;
238
239 if (!ofnode_valid(dsi_np))
240 return -EINVAL;
241
242 rk628->dsi0.id = 0;
243 rk628->dsi0.channel = 0;
244 rk628->dsi0.rk628 = rk628;
245
246 rk628->dsi0.lanes = ofnode_read_u32_default(dsi_np, "dsi,lanes", 4);
247 if (ofnode_read_bool(dsi_np, "dsi,video-mode"))
248 rk628->dsi0.mode_flags |= RK628_MIPI_DSI_MODE_LPM | RK628_MIPI_DSI_MODE_VIDEO |
249 RK628_MIPI_DSI_MODE_VIDEO_BURST;
250 else
251 rk628->dsi0.mode_flags |= RK628_MIPI_DSI_MODE_LPM;
252
253 if (ofnode_read_bool(dsi_np, "dsi,eotp"))
254 rk628->dsi0.mode_flags |= RK628_MIPI_DSI_MODE_EOT_PACKET;
255
256 if (ofnode_read_bool(dsi_np, "dsi,clk-non-continuous"))
257 rk628->dsi0.mode_flags |= RK628_MIPI_DSI_CLOCK_NON_CONTINUOUS;
258
259 string = ofnode_read_string(dsi_np, "dsi,format");
260 if (!strcmp(string, "rgb666")) {
261 rk628->dsi0.bus_format = RK628_MIPI_DSI_FMT_RGB666;
262 rk628->dsi0.bpp = 24;
263 } else if (!strcmp(string, "rgb666-packed")) {
264 rk628->dsi0.bus_format = RK628_MIPI_DSI_FMT_RGB666_PACKED;
265 rk628->dsi0.bpp = 18;
266 } else if (!strcmp(string, "rgb565")) {
267 rk628->dsi0.bus_format = RK628_MIPI_DSI_FMT_RGB565;
268 rk628->dsi0.bpp = 16;
269 } else {
270 rk628->dsi0.bus_format = RK628_MIPI_DSI_FMT_RGB888;
271 rk628->dsi0.bpp = 24;
272 }
273
274 if (ofnode_read_bool(dsi_np, "rockchip,dual-channel")) {
275 rk628->dsi0.master = false;
276 rk628->dsi0.slave = true;
277
278 memcpy(&rk628->dsi1, &rk628->dsi0, sizeof(struct rk628_dsi));
279 rk628->dsi1.id = 1;
280 rk628->dsi1.master = true;
281 rk628->dsi1.slave = false;
282 }
283
284 ret = rk628_panel_info_get(rk628, dsi_np);
285 if (ret)
286 return ret;
287
288
289 return 0;
290 }
291
genif_wait_w_pld_fifo_not_full(struct rk628 * rk628,const struct rk628_dsi * dsi)292 static int genif_wait_w_pld_fifo_not_full(struct rk628 *rk628,
293 const struct rk628_dsi *dsi)
294 {
295 u32 sts = 0;
296 int ret;
297 unsigned int dsi_base;
298
299 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
300
301 ret = rk628_read_poll_timeout(rk628, dsi_base + DSI_CMD_PKT_STATUS,
302 sts, !(sts & GEN_PLD_W_FULL), 0, 1000);
303 if (ret < 0) {
304 printf("rk628 generic write payload fifo is full\n");
305 return ret;
306 }
307
308 return 0;
309 }
310
genif_wait_cmd_fifo_not_full(struct rk628 * rk628,const struct rk628_dsi * dsi)311 static int genif_wait_cmd_fifo_not_full(struct rk628 *rk628,
312 const struct rk628_dsi *dsi)
313 {
314 u32 sts = 0;
315 int ret = 0;
316 unsigned int dsi_base;
317
318 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
319
320 ret = rk628_read_poll_timeout(rk628, dsi_base + DSI_CMD_PKT_STATUS,
321 sts, !(sts & GEN_CMD_FULL),
322 0, 1000);
323 if (ret < 0) {
324 printf("rk628 generic write cmd fifo is full\n");
325 return ret;
326 }
327
328 return 0;
329 }
330
genif_wait_write_fifo_empty(struct rk628 * rk628,const struct rk628_dsi * dsi)331 static int genif_wait_write_fifo_empty(struct rk628 *rk628, const struct rk628_dsi *dsi)
332 {
333 u32 sts = 0;
334 u32 mask;
335 int ret;
336 unsigned int dsi_base;
337
338 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
339
340 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
341
342 ret = rk628_read_poll_timeout(rk628, dsi_base + DSI_CMD_PKT_STATUS,
343 sts, (sts & mask) == mask, 0, 1000);
344 if (ret < 0) {
345 printf("rk628 generic write fifo is full\n");
346 return ret;
347 }
348
349 return 0;
350 }
351
rk628_dsi_read_from_fifo(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct rk628_mipi_dsi_msg * msg)352 static int rk628_dsi_read_from_fifo(struct rk628 *rk628,
353 const struct rk628_dsi *dsi,
354 const struct rk628_mipi_dsi_msg *msg)
355 {
356 u8 *payload = msg->rx_buf;
357 unsigned int vrefresh = 60;
358 u16 length;
359 u32 val = 0;
360 int ret;
361 unsigned int dsi_base;
362
363 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
364
365 ret = rk628_read_poll_timeout(rk628, dsi_base + DSI_CMD_PKT_STATUS,
366 val, !(val & GEN_RD_CMD_BUSY),
367 0, DIV_ROUND_UP(1000000, vrefresh));
368 if (ret) {
369 printf("rk628 entire response isn't stored in the FIFO\n");
370 return ret;
371 }
372
373 /* Receive payload */
374 for (length = msg->rx_len; length; length -= 4) {
375 dsi_read(rk628, dsi, DSI_CMD_PKT_STATUS, &val);
376 if (val & GEN_PLD_R_EMPTY)
377 ret = -ETIMEDOUT;
378 if (ret) {
379 printf("rk628 dsi Read payload FIFO is empty\n");
380 return ret;
381 }
382
383 dsi_read(rk628, dsi, DSI_GEN_PLD_DATA, &val);
384
385 switch (length) {
386 case 3:
387 payload[2] = (val >> 16) & 0xff;
388 /* Fall through */
389 case 2:
390 payload[1] = (val >> 8) & 0xff;
391 /* Fall through */
392 case 1:
393 payload[0] = val & 0xff;
394 return 0;
395 }
396
397 payload[0] = (val >> 0) & 0xff;
398 payload[1] = (val >> 8) & 0xff;
399 payload[2] = (val >> 16) & 0xff;
400 payload[3] = (val >> 24) & 0xff;
401 payload += 4;
402 }
403
404 return 0;
405 }
406
407 /**
408 * rk628_mipi_dsi_packet_format_is_short - check if a packet is of the short format
409 * @type: MIPI DSI data type of the packet
410 *
411 * Return: true if the packet for the given data type is a short packet, false
412 * otherwise.
413 */
rk628_mipi_dsi_packet_format_is_short(u8 type)414 static bool rk628_mipi_dsi_packet_format_is_short(u8 type)
415 {
416 switch (type) {
417 case RK628_MIPI_DSI_V_SYNC_START:
418 case RK628_MIPI_DSI_V_SYNC_END:
419 case RK628_MIPI_DSI_H_SYNC_START:
420 case RK628_MIPI_DSI_H_SYNC_END:
421 case RK628_MIPI_DSI_END_OF_TRANSMISSION:
422 case RK628_MIPI_DSI_COLOR_MODE_OFF:
423 case RK628_MIPI_DSI_COLOR_MODE_ON:
424 case RK628_MIPI_DSI_SHUTDOWN_PERIPHERAL:
425 case RK628_MIPI_DSI_TURN_ON_PERIPHERAL:
426 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
427 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
428 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
429 case RK628_MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
430 case RK628_MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
431 case RK628_MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
432 case RK628_MIPI_DSI_DCS_SHORT_WRITE:
433 case RK628_MIPI_DSI_DCS_SHORT_WRITE_PARAM:
434 case RK628_MIPI_DSI_DCS_READ:
435 case RK628_MIPI_DSI_DCS_COMPRESSION_MODE:
436 case RK628_MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
437 return true;
438 }
439
440 return false;
441 }
442
443 /**
444 * rk628_mipi_dsi_packet_format_is_long - check if a packet is of the long format
445 * @type: MIPI DSI data type of the packet
446 *
447 * Return: true if the packet for the given data type is a long packet, false
448 * otherwise.
449 */
rk628_mipi_dsi_packet_format_is_long(u8 type)450 static bool rk628_mipi_dsi_packet_format_is_long(u8 type)
451 {
452 switch (type) {
453 case RK628_MIPI_DSI_PPS_LONG_WRITE:
454 case RK628_MIPI_DSI_NULL_PACKET:
455 case RK628_MIPI_DSI_BLANKING_PACKET:
456 case RK628_MIPI_DSI_GENERIC_LONG_WRITE:
457 case RK628_MIPI_DSI_DCS_LONG_WRITE:
458 case RK628_MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
459 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
460 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
461 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_30:
462 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_36:
463 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12:
464 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_16:
465 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_18:
466 case RK628_MIPI_DSI_PIXEL_STREAM_3BYTE_18:
467 case RK628_MIPI_DSI_PACKED_PIXEL_STREAM_24:
468 return true;
469 }
470
471 return false;
472 }
473
474 /**
475 * rk628_mipi_dsi_create_packet - create a packet from a message according to the
476 * DSI protocol
477 * @packet: pointer to a DSI packet structure
478 * @msg: message to translate into a packet
479 *
480 * Return: 0 on success or a negative error code on failure.
481 */
rk628_mipi_dsi_create_packet(struct rk628_mipi_dsi_packet * packet,const struct rk628_mipi_dsi_msg * msg)482 static int rk628_mipi_dsi_create_packet(struct rk628_mipi_dsi_packet *packet,
483 const struct rk628_mipi_dsi_msg *msg)
484 {
485 if (!packet || !msg)
486 return -EINVAL;
487
488 /* do some minimum sanity checking */
489 if (!rk628_mipi_dsi_packet_format_is_short(msg->type) &&
490 !rk628_mipi_dsi_packet_format_is_long(msg->type))
491 return -EINVAL;
492
493 if (msg->channel > 3)
494 return -EINVAL;
495
496 memset(packet, 0, sizeof(*packet));
497 packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f);
498
499 /* TODO: compute ECC if hardware support is not available */
500
501 /*
502 * Long write packets contain the word count in header bytes 1 and 2.
503 * The payload follows the header and is word count bytes long.
504 *
505 * Short write packets encode up to two parameters in header bytes 1
506 * and 2.
507 */
508 if (rk628_mipi_dsi_packet_format_is_long(msg->type)) {
509 packet->header[1] = (msg->tx_len >> 0) & 0xff;
510 packet->header[2] = (msg->tx_len >> 8) & 0xff;
511
512 packet->payload_length = msg->tx_len;
513 packet->payload = msg->tx_buf;
514 } else {
515 const u8 *tx = msg->tx_buf;
516
517 packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0;
518 packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0;
519 }
520
521 packet->size = sizeof(packet->header) + packet->payload_length;
522
523 return 0;
524 }
525
rk628_dsi_transfer(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct rk628_mipi_dsi_msg * msg)526 static int rk628_dsi_transfer(struct rk628 *rk628, const struct rk628_dsi *dsi,
527 const struct rk628_mipi_dsi_msg *msg)
528 {
529 struct rk628_mipi_dsi_packet packet;
530 int ret;
531 u32 val;
532
533 if (msg->flags & RK628_MIPI_DSI_MSG_REQ_ACK)
534 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG,
535 ACK_RQST_EN, ACK_RQST_EN);
536
537 if (msg->flags & RK628_MIPI_DSI_MSG_USE_LPM) {
538 dsi_update_bits(rk628, dsi, DSI_VID_MODE_CFG,
539 LP_CMD_EN, LP_CMD_EN);
540 } else {
541 dsi_update_bits(rk628, dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0);
542 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL,
543 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS);
544 }
545
546 switch (msg->type) {
547 case RK628_MIPI_DSI_SHUTDOWN_PERIPHERAL:
548 //return rk628_dsi_shutdown_peripheral(dsi);
549 case RK628_MIPI_DSI_TURN_ON_PERIPHERAL:
550 //return rk628_dsi_turn_on_peripheral(dsi);
551 case RK628_MIPI_DSI_DCS_SHORT_WRITE:
552 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,
553 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
554 DCS_SW_0P_TX : 0);
555 break;
556 case RK628_MIPI_DSI_DCS_SHORT_WRITE_PARAM:
557 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,
558 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
559 DCS_SW_1P_TX : 0);
560 break;
561 case RK628_MIPI_DSI_DCS_LONG_WRITE:
562 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_LW_TX,
563 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
564 DCS_LW_TX : 0);
565 break;
566 case RK628_MIPI_DSI_DCS_READ:
567 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,
568 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
569 DCS_SR_0P_TX : 0);
570 break;
571 case RK628_MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
572 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE,
573 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
574 MAX_RD_PKT_SIZE : 0);
575 break;
576 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
577 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,
578 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
579 GEN_SW_0P_TX : 0);
580 break;
581 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
582 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,
583 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
584 GEN_SW_1P_TX : 0);
585 break;
586 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
587 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,
588 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
589 GEN_SW_2P_TX : 0);
590 break;
591 case RK628_MIPI_DSI_GENERIC_LONG_WRITE:
592 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_LW_TX,
593 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ?
594 GEN_LW_TX : 0);
595 break;
596 case RK628_MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
597 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,
598 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ? GEN_SR_0P_TX : 0);
599 break;
600 case RK628_MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
601 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,
602 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ? GEN_SR_1P_TX : 0);
603 break;
604 case RK628_MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
605 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,
606 msg->flags & RK628_MIPI_DSI_MSG_USE_LPM ? GEN_SR_2P_TX : 0);
607 break;
608 default:
609 return -EINVAL;
610 }
611
612 /* create a packet to the DSI protocol */
613 ret = rk628_mipi_dsi_create_packet(&packet, msg);
614 if (ret) {
615 printf("rk628 dsi failed to create packet\n");
616 return ret;
617 }
618
619 /* Send payload */
620 while (packet.payload_length >= 4) {
621 /*
622 * Alternatively, you can always keep the FIFO
623 * nearly full by monitoring the FIFO state until
624 * it is not full, and then writea single word of data.
625 * This solution is more resource consuming
626 * but it simultaneously avoids FIFO starvation,
627 * making it possible to use FIFO sizes smaller than
628 * the amount of data of the longest packet to be written.
629 */
630 ret = genif_wait_w_pld_fifo_not_full(rk628, dsi);
631 if (ret)
632 return ret;
633
634 val = get_unaligned_le32(packet.payload);
635
636 dsi_write(rk628, dsi, DSI_GEN_PLD_DATA, val);
637
638
639 packet.payload += 4;
640 packet.payload_length -= 4;
641 }
642
643 val = 0;
644 switch (packet.payload_length) {
645 case 3:
646 val |= packet.payload[2] << 16;
647 /* Fall through */
648 case 2:
649 val |= packet.payload[1] << 8;
650 /* Fall through */
651 case 1:
652 val |= packet.payload[0];
653
654 dsi_write(rk628, dsi, DSI_GEN_PLD_DATA, val);
655 break;
656 }
657
658 ret = genif_wait_cmd_fifo_not_full(rk628, dsi);
659 if (ret)
660 return ret;
661
662 /* Send packet header */
663 val = get_unaligned_le32(packet.header);
664
665 dsi_write(rk628, dsi, DSI_GEN_HDR, val);
666
667 ret = genif_wait_write_fifo_empty(rk628, dsi);
668 if (ret)
669 return ret;
670
671 if (msg->rx_len) {
672 ret = rk628_dsi_read_from_fifo(rk628, dsi, msg);
673 if (ret < 0)
674 return ret;
675 }
676
677 if (dsi->slave) {
678 const struct rk628_dsi *dsi1 = &rk628->dsi1;
679
680 rk628_dsi_transfer(rk628, dsi1, msg);
681 }
682
683 return msg->tx_len;
684 }
685
rk628_mipi_dsi_generic_write(struct rk628 * rk628,const void * payload,size_t size)686 static int rk628_mipi_dsi_generic_write(struct rk628 *rk628,
687 const void *payload, size_t size)
688 {
689 const struct rk628_dsi *dsi = &rk628->dsi0;
690 struct rk628_mipi_dsi_msg msg;
691
692 memset(&msg, 0, sizeof(msg));
693 msg.channel = dsi->channel;
694 msg.tx_buf = payload;
695 msg.tx_len = size;
696 msg.rx_len = 0;
697
698 switch (size) {
699 case 0:
700 msg.type = RK628_MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
701 break;
702
703 case 1:
704 msg.type = RK628_MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
705 break;
706 case 2:
707 msg.type = RK628_MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
708 break;
709 default:
710 msg.type = RK628_MIPI_DSI_GENERIC_LONG_WRITE;
711 break;
712 }
713
714 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_LPM)
715 msg.flags |= RK628_MIPI_DSI_MSG_USE_LPM;
716
717 return rk628_dsi_transfer(rk628, dsi, &msg);
718 }
719
rk628_mipi_dsi_dcs_write_buffer(struct rk628 * rk628,const void * data,size_t len)720 static int rk628_mipi_dsi_dcs_write_buffer(struct rk628 *rk628,
721 const void *data, size_t len)
722 {
723 const struct rk628_dsi *dsi = &rk628->dsi0;
724 struct rk628_mipi_dsi_msg msg;
725
726 memset(&msg, 0, sizeof(msg));
727 msg.channel = dsi->channel;
728 msg.tx_buf = data;
729 msg.tx_len = len;
730 msg.rx_len = 0;
731
732 switch (len) {
733 case 0:
734 return -EINVAL;
735 case 1:
736 msg.type = RK628_MIPI_DSI_DCS_SHORT_WRITE;
737 break;
738 case 2:
739 msg.type = RK628_MIPI_DSI_DCS_SHORT_WRITE_PARAM;
740 break;
741 default:
742 msg.type = RK628_MIPI_DSI_DCS_LONG_WRITE;
743 break;
744 }
745
746 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_LPM)
747 msg.flags |= RK628_MIPI_DSI_MSG_USE_LPM;
748
749 return rk628_dsi_transfer(rk628, dsi, &msg);
750 }
751
rk628_mipi_dsi_dcs_read(struct rk628 * rk628,u8 cmd,void * data,size_t len)752 static __maybe_unused int rk628_mipi_dsi_dcs_read(struct rk628 *rk628, u8 cmd,
753 void *data, size_t len)
754 {
755 const struct rk628_dsi *dsi = &rk628->dsi0;
756 struct rk628_mipi_dsi_msg msg;
757
758 memset(&msg, 0, sizeof(msg));
759 msg.channel = dsi->channel;
760 msg.type = RK628_MIPI_DSI_DCS_READ;
761 msg.tx_buf = &cmd;
762 msg.tx_len = 1;
763 msg.rx_buf = data;
764 msg.rx_len = len;
765
766 return rk628_dsi_transfer(rk628, dsi, &msg);
767 }
768
769 static int
panel_simple_xfer_dsi_cmd_seq(struct rk628 * rk628,struct panel_cmds * cmds)770 panel_simple_xfer_dsi_cmd_seq(struct rk628 *rk628, struct panel_cmds *cmds)
771 {
772 u16 i;
773 int err;
774
775 if (!cmds)
776 return 0;
777
778 for (i = 0; i < cmds->cmd_cnt; i++) {
779 struct cmd_desc *cmd = &cmds->cmds[i];
780
781 switch (cmd->dchdr.dtype) {
782 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
783 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
784 case RK628_MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
785 case RK628_MIPI_DSI_GENERIC_LONG_WRITE:
786 err = rk628_mipi_dsi_generic_write(rk628, cmd->payload,
787 cmd->dchdr.dlen);
788 break;
789 case RK628_MIPI_DSI_DCS_SHORT_WRITE:
790 case RK628_MIPI_DSI_DCS_SHORT_WRITE_PARAM:
791 case RK628_MIPI_DSI_DCS_LONG_WRITE:
792 err = rk628_mipi_dsi_dcs_write_buffer(rk628, cmd->payload,
793 cmd->dchdr.dlen);
794 break;
795 default:
796 printf("rk628 dsi panel cmd desc invalid data type\n");
797 return -EINVAL;
798 }
799
800 if (err < 0)
801 printf("rk628 dsi failed to write cmd\n");
802
803 if (cmd->dchdr.wait)
804 mdelay(cmd->dchdr.wait);
805 }
806
807 return 0;
808 }
809
rk628_dsi_get_lane_rate(const struct rk628_dsi * dsi)810 static u32 rk628_dsi_get_lane_rate(const struct rk628_dsi *dsi)
811 {
812 const struct drm_display_mode *mode = &dsi->rk628->dst_mode;
813 ofnode dsi_np;
814 u32 lane_rate, value;
815 u32 max_lane_rate = 1500;
816 u8 bpp, lanes;
817
818 dsi_np = dev_read_subnode(dsi->rk628->dev, "rk628-dsi-out");
819 if (!ofnode_valid(dsi_np))
820 dsi_np = dev_read_subnode(dsi->rk628->dev, "rk628-dsi");
821 if (ofnode_valid(dsi_np) && !ofnode_read_u32(dsi_np, "rockchip,lane-mbps", &value)) {
822 lane_rate = value;
823 } else {
824 bpp = dsi->bpp;
825 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
826 lane_rate = mode->clock / 1000 * bpp / lanes;
827 lane_rate = DIV_ROUND_UP(lane_rate * 5, 4);
828 }
829
830 if (lane_rate > max_lane_rate)
831 lane_rate = max_lane_rate;
832
833 return lane_rate;
834 }
835
testif_testclk_assert(struct rk628 * rk628,const struct rk628_dsi * dsi)836 static void testif_testclk_assert(struct rk628 *rk628,
837 const struct rk628_dsi *dsi)
838 {
839 rk628_i2c_update_bits(rk628, dsi->id ?
840 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
841 PHY_TESTCLK, PHY_TESTCLK);
842 udelay(1);
843 }
844
testif_testclk_deassert(struct rk628 * rk628,const struct rk628_dsi * dsi)845 static void testif_testclk_deassert(struct rk628 *rk628,
846 const struct rk628_dsi *dsi)
847 {
848 rk628_i2c_update_bits(rk628, dsi->id ?
849 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
850 PHY_TESTCLK, 0);
851 udelay(1);
852 }
853
testif_testclr_assert(struct rk628 * rk628,const struct rk628_dsi * dsi)854 static void testif_testclr_assert(struct rk628 *rk628,
855 const struct rk628_dsi *dsi)
856 {
857 rk628_i2c_update_bits(rk628, dsi->id ?
858 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
859 PHY_TESTCLR, PHY_TESTCLR);
860 udelay(1);
861 }
862
testif_testclr_deassert(struct rk628 * rk628,const struct rk628_dsi * dsi)863 static void testif_testclr_deassert(struct rk628 *rk628,
864 const struct rk628_dsi *dsi)
865 {
866 rk628_i2c_update_bits(rk628, dsi->id ?
867 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
868 PHY_TESTCLR, 0);
869 udelay(1);
870 }
871
testif_set_data(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 data)872 static void testif_set_data(struct rk628 *rk628,
873 const struct rk628_dsi *dsi, u8 data)
874 {
875 rk628_i2c_update_bits(rk628, dsi->id ?
876 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
877 PHY_TESTDIN_MASK, PHY_TESTDIN(data));
878 udelay(1);
879 }
880
testif_testen_assert(struct rk628 * rk628,const struct rk628_dsi * dsi)881 static void testif_testen_assert(struct rk628 *rk628,
882 const struct rk628_dsi *dsi)
883 {
884 rk628_i2c_update_bits(rk628, dsi->id ?
885 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
886 PHY_TESTEN, PHY_TESTEN);
887 udelay(1);
888 }
889
testif_testen_deassert(struct rk628 * rk628,const struct rk628_dsi * dsi)890 static void testif_testen_deassert(struct rk628 *rk628,
891 const struct rk628_dsi *dsi)
892 {
893 rk628_i2c_update_bits(rk628, dsi->id ?
894 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
895 PHY_TESTEN, 0);
896 udelay(1);
897 }
898
testif_test_code_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 test_code)899 static void testif_test_code_write(struct rk628 *rk628,
900 const struct rk628_dsi *dsi, u8 test_code)
901 {
902 testif_testclk_assert(rk628, dsi);
903 testif_set_data(rk628, dsi, test_code);
904 testif_testen_assert(rk628, dsi);
905 testif_testclk_deassert(rk628, dsi);
906 testif_testen_deassert(rk628, dsi);
907 }
908
testif_test_data_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 test_data)909 static void testif_test_data_write(struct rk628 *rk628,
910 const struct rk628_dsi *dsi, u8 test_data)
911 {
912 testif_testclk_deassert(rk628, dsi);
913 testif_set_data(rk628, dsi, test_data);
914 testif_testclk_assert(rk628, dsi);
915 }
916
testif_get_data(struct rk628 * rk628,const struct rk628_dsi * dsi)917 static u8 testif_get_data(struct rk628 *rk628, const struct rk628_dsi *dsi)
918 {
919 u32 data = 0;
920
921 rk628_i2c_read(rk628, dsi->id ? GRF_DPHY1_STATUS : GRF_DPHY0_STATUS, &data);
922
923 return data >> PHY_TESTDOUT_SHIFT;
924 }
925
testif_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 reg,u8 value)926 static void testif_write(struct rk628 *rk628, const struct rk628_dsi *dsi,
927 u8 reg, u8 value)
928 {
929 u8 monitor_data;
930
931 testif_test_code_write(rk628, dsi, reg);
932 testif_test_data_write(rk628, dsi, value);
933 monitor_data = testif_get_data(rk628, dsi);
934 printf("rk628 dsi monitor_data: 0x%x\n", monitor_data);
935 }
936
testif_set_timing(const struct rk628_dsi * dsi,u8 addr,u8 max,u8 val)937 static void testif_set_timing(const struct rk628_dsi *dsi, u8 addr,
938 u8 max, u8 val)
939 {
940 struct rk628 *rk628 = dsi->rk628;
941
942 if (val > max)
943 return;
944
945 testif_write(rk628, dsi, addr, (max + 1) | val);
946 }
947
mipi_dphy_set_timing(const struct rk628_dsi * dsi)948 static void mipi_dphy_set_timing(const struct rk628_dsi *dsi)
949 {
950 const struct {
951 unsigned int min_lane_mbps;
952 unsigned int max_lane_mbps;
953 u8 clk_lp;
954 u8 clk_hs_prepare;
955 u8 clk_hs_zero;
956 u8 clk_hs_trail;
957 u8 clk_post;
958 u8 data_lp;
959 u8 data_hs_prepare;
960 u8 data_hs_zero;
961 u8 data_hs_trail;
962 } timing_table[] = {
963 {800, 899, 0x07, 0x30, 0x25, 0x3c, 0x0f, 0x07, 0x40, 0x09, 0x40},
964 {1100, 1249, 0x0a, 0x43, 0x2c, 0x50, 0x0f, 0x0a, 0x43, 0x10, 0x55},
965 {1250, 1349, 0x0b, 0x43, 0x2c, 0x50, 0x0f, 0x0b, 0x53, 0x10, 0x5b},
966 {1350, 1449, 0x0c, 0x43, 0x36, 0x60, 0x0f, 0x0c, 0x53, 0x10, 0x65},
967 {1450, 1500, 0x0f, 0x60, 0x31, 0x60, 0x0f, 0x0e, 0x60, 0x11, 0x6a}
968 };
969 unsigned int index;
970
971 if (dsi->lane_mbps < timing_table[0].min_lane_mbps)
972 return;
973
974 for (index = 0; index < ARRAY_SIZE(timing_table); index++)
975 if (dsi->lane_mbps >= timing_table[index].min_lane_mbps &&
976 dsi->lane_mbps < timing_table[index].max_lane_mbps)
977 break;
978
979 if (index == ARRAY_SIZE(timing_table))
980 --index;
981
982 if (dsi->lane_mbps < timing_table[index].max_lane_mbps)
983 return;
984
985 testif_set_timing(dsi, 0x60, 0x3f, timing_table[index].clk_lp);
986 testif_set_timing(dsi, 0x61, 0x7f, timing_table[index].clk_hs_prepare);
987 testif_set_timing(dsi, 0x62, 0x3f, timing_table[index].clk_hs_zero);
988 testif_set_timing(dsi, 0x63, 0x7f, timing_table[index].clk_hs_trail);
989 testif_set_timing(dsi, 0x65, 0x0f, timing_table[index].clk_post);
990 testif_set_timing(dsi, 0x70, 0x3f, timing_table[index].data_lp);
991 testif_set_timing(dsi, 0x71, 0x7f, timing_table[index].data_hs_prepare);
992 testif_set_timing(dsi, 0x72, 0x3f, timing_table[index].data_hs_zero);
993 testif_set_timing(dsi, 0x73, 0x7f, timing_table[index].data_hs_trail);
994 }
995
mipi_dphy_init(struct rk628 * rk628,const struct rk628_dsi * dsi)996 static void mipi_dphy_init(struct rk628 *rk628, const struct rk628_dsi *dsi)
997 {
998 const struct {
999 unsigned long max_lane_mbps;
1000 u8 hsfreqrange;
1001 } hsfreqrange_table[] = {
1002 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
1003 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
1004 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
1005 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
1006 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
1007 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
1008 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
1009 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
1010 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
1011 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
1012 };
1013 u8 hsfreqrange;
1014 unsigned int index;
1015
1016 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
1017 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
1018 break;
1019
1020 if (index == ARRAY_SIZE(hsfreqrange_table))
1021 --index;
1022
1023 hsfreqrange = hsfreqrange_table[index].hsfreqrange;
1024 testif_write(rk628, dsi, 0x44, HSFREQRANGE(hsfreqrange));
1025
1026 if (rk628->version == RK628F_VERSION)
1027 mipi_dphy_set_timing(dsi);
1028 }
1029
mipi_dphy_power_on(struct rk628 * rk628,const struct rk628_dsi * dsi)1030 static void mipi_dphy_power_on(struct rk628 *rk628, const struct rk628_dsi *dsi)
1031 {
1032 unsigned int dsi_base;
1033 unsigned int val = 0, mask;
1034 int ret;
1035
1036 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
1037
1038 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
1039 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
1040 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0);
1041 testif_testclr_assert(rk628, dsi);
1042
1043 /* Set all REQUEST inputs to zero */
1044 rk628_i2c_update_bits(rk628, dsi->id ?
1045 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
1046 FORCERXMODE_MASK | FORCETXSTOPMODE_MASK,
1047 FORCETXSTOPMODE(0) | FORCERXMODE(0));
1048 udelay(1);
1049
1050 testif_testclr_deassert(rk628, dsi);
1051
1052 mipi_dphy_init(rk628, dsi);
1053
1054 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ,
1055 PHY_ENABLECLK, PHY_ENABLECLK);
1056 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ,
1057 PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
1058 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
1059 udelay(2000);
1060
1061 rk628_combtxphy_power_on(rk628);
1062
1063 ret = rk628_read_poll_timeout(rk628, dsi_base + DSI_PHY_STATUS,
1064 val, val & PHY_LOCK, 0, 1000);
1065 if (ret < 0)
1066 printf("rk628 dsi PHY is not locked\n");
1067
1068 udelay(200);
1069
1070 mask = PHY_STOPSTATELANE;
1071 ret = rk628_read_poll_timeout(rk628, dsi_base + DSI_PHY_STATUS,
1072 val, (val & mask) == mask,
1073 0, 1000);
1074 if (ret < 0)
1075 printf("rk628 dsi lane module is not in stop state\n");
1076
1077 udelay(10);
1078 }
1079
rk628_dsi0_reset_control_assert(struct rk628 * rk628)1080 static void rk628_dsi0_reset_control_assert(struct rk628 *rk628)
1081 {
1082 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x400040);
1083 }
1084
rk628_dsi0_reset_control_deassert(struct rk628 * rk628)1085 static void rk628_dsi0_reset_control_deassert(struct rk628 *rk628)
1086 {
1087 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x400000);
1088 }
1089
rk628_dsi1_reset_control_assert(struct rk628 * rk628)1090 static void rk628_dsi1_reset_control_assert(struct rk628 *rk628)
1091 {
1092 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x800080);
1093 }
1094
rk628_dsi1_reset_control_deassert(struct rk628 * rk628)1095 static void rk628_dsi1_reset_control_deassert(struct rk628 *rk628)
1096 {
1097 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x800000);
1098 }
1099
rk628_dsi_bridge_pre_enable(struct rk628 * rk628,const struct rk628_dsi * dsi)1100 static void rk628_dsi_bridge_pre_enable(struct rk628 *rk628,
1101 const struct rk628_dsi *dsi)
1102 {
1103 u32 val;
1104
1105 dsi_write(rk628, dsi, DSI_PWR_UP, RESET);
1106 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_COMMAND_MODE));
1107
1108 val = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);
1109 dsi_write(rk628, dsi, DSI_CLKMGR_CFG,
1110 TO_CLK_DIVISION(10) | TX_ESC_CLK_DIVISION(val));
1111
1112 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN;
1113 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_EOT_PACKET)
1114 val &= ~EOTP_TX_EN;
1115
1116 dsi_write(rk628, dsi, DSI_PCKHDL_CFG, val);
1117
1118 dsi_write(rk628, dsi, DSI_TO_CNT_CFG,
1119 HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
1120 dsi_write(rk628, dsi, DSI_BTA_TO_CNT, 0xd00);
1121 dsi_write(rk628, dsi, DSI_PHY_TMR_CFG,
1122 PHY_HS2LP_TIME(0x14) | PHY_LP2HS_TIME(0x10) |
1123 MAX_RD_TIME(10000));
1124 dsi_write(rk628, dsi, DSI_PHY_TMR_LPCLK_CFG,
1125 PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));
1126 dsi_write(rk628, dsi, DSI_PHY_IF_CFG,
1127 PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes - 1));
1128
1129 mipi_dphy_power_on(rk628, dsi);
1130
1131 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP);
1132 }
1133
rk628_dsi_set_vid_mode(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct drm_display_mode * mode)1134 static void rk628_dsi_set_vid_mode(struct rk628 *rk628,
1135 const struct rk628_dsi *dsi,
1136 const struct drm_display_mode *mode)
1137 {
1138 unsigned int lanebyteclk = (dsi->lane_mbps * 1000L) >> 3;
1139 unsigned int dpipclk = mode->clock;
1140 u32 hline, hsa, hbp, hline_time, hsa_time, hbp_time;
1141 u32 vactive, vsa, vfp, vbp;
1142 u32 val;
1143 int pkt_size;
1144
1145 val = LP_HFP_EN | LP_HBP_EN | LP_VACT_EN | LP_VFP_EN | LP_VBP_EN |
1146 LP_VSA_EN;
1147
1148 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_HFP)
1149 val &= ~LP_HFP_EN;
1150
1151 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_HBP)
1152 val &= ~LP_HBP_EN;
1153
1154 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_BURST)
1155 val |= VID_MODE_TYPE_BURST;
1156 else if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
1157 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
1158 else
1159 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
1160
1161 dsi_write(rk628, dsi, DSI_VID_MODE_CFG, val);
1162
1163 if (dsi->mode_flags & RK628_MIPI_DSI_CLOCK_NON_CONTINUOUS)
1164 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL,
1165 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL);
1166
1167 if (dsi->slave || dsi->master)
1168 pkt_size = VID_PKT_SIZE(mode->hdisplay / 2);
1169 else
1170 pkt_size = VID_PKT_SIZE(mode->hdisplay);
1171
1172 dsi_write(rk628, dsi, DSI_VID_PKT_SIZE, pkt_size);
1173
1174 vactive = mode->vdisplay;
1175 vsa = mode->vsync_end - mode->vsync_start;
1176 vfp = mode->vsync_start - mode->vdisplay;
1177 vbp = mode->vtotal - mode->vsync_end;
1178 hsa = mode->hsync_end - mode->hsync_start;
1179 hbp = mode->htotal - mode->hsync_end;
1180 hline = mode->htotal;
1181
1182 //hline_time = hline * lanebyteclk / dpipclk;
1183 hline_time = DIV_ROUND_CLOSEST(hline * lanebyteclk, dpipclk);
1184 dsi_write(rk628, dsi, DSI_VID_HLINE_TIME,
1185 VID_HLINE_TIME(hline_time));
1186 //hsa_time = hsa * lanebyteclk / dpipclk;
1187 hsa_time = DIV_ROUND_CLOSEST(hsa * lanebyteclk, dpipclk);
1188 dsi_write(rk628, dsi, DSI_VID_HSA_TIME, VID_HSA_TIME(hsa_time));
1189 //hbp_time = hbp * lanebyteclk / dpipclk;
1190 hbp_time = DIV_ROUND_CLOSEST(hbp * lanebyteclk, dpipclk);
1191 dsi_write(rk628, dsi, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));
1192
1193 dsi_write(rk628, dsi, DSI_VID_VACTIVE_LINES, vactive);
1194 dsi_write(rk628, dsi, DSI_VID_VSA_LINES, vsa);
1195 dsi_write(rk628, dsi, DSI_VID_VFP_LINES, vfp);
1196 dsi_write(rk628, dsi, DSI_VID_VBP_LINES, vbp);
1197
1198 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_VIDEO_MODE));
1199 }
1200
rk628_dsi_set_cmd_mode(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct drm_display_mode * mode)1201 static void rk628_dsi_set_cmd_mode(struct rk628 *rk628,
1202 const struct rk628_dsi *dsi,
1203 const struct drm_display_mode *mode)
1204 {
1205 int cmd_size;
1206
1207 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);
1208
1209 /* rk628: The maximum capacity of dsi memory is 2048*32 bits */
1210 if (mode->hdisplay > 2048)
1211 cmd_size = EDPI_ALLOWED_CMD_SIZE(mode->hdisplay / 2);
1212 else
1213 cmd_size = EDPI_ALLOWED_CMD_SIZE(mode->hdisplay);
1214
1215 dsi_write(rk628, dsi, DSI_EDPI_CMD_SIZE, cmd_size);
1216
1217 if (dsi->mode_flags & RK628_MIPI_DSI_CLOCK_NON_CONTINUOUS)
1218 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL,
1219 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL);
1220
1221 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_COMMAND_MODE));
1222 }
1223
rk628_dsi_bridge_enable(struct rk628 * rk628,const struct rk628_dsi * dsi)1224 static void rk628_dsi_bridge_enable(struct rk628 *rk628,
1225 const struct rk628_dsi *dsi)
1226 {
1227 u32 val;
1228 const struct drm_display_mode *mode = &rk628->dst_mode;
1229
1230 dsi_write(rk628, dsi, DSI_PWR_UP, RESET);
1231
1232 switch (dsi->bus_format) {
1233 case RK628_MIPI_DSI_FMT_RGB666:
1234 val = DPI_COLOR_CODING(DPI_COLOR_CODING_18BIT_2) |
1235 LOOSELY18_EN;
1236 break;
1237 case RK628_MIPI_DSI_FMT_RGB666_PACKED:
1238 val = DPI_COLOR_CODING(DPI_COLOR_CODING_18BIT_1);
1239 break;
1240 case RK628_MIPI_DSI_FMT_RGB565:
1241 val = DPI_COLOR_CODING(DPI_COLOR_CODING_16BIT_1);
1242 break;
1243 case RK628_MIPI_DSI_FMT_RGB888:
1244 default:
1245 val = DPI_COLOR_CODING(DPI_COLOR_CODING_24BIT);
1246 break;
1247 }
1248
1249 dsi_write(rk628, dsi, DSI_DPI_COLOR_CODING, val);
1250
1251 val = 0;
1252 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1253 val |= VSYNC_ACTIVE_LOW;
1254 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1255 val |= HSYNC_ACTIVE_LOW;
1256
1257 dsi_write(rk628, dsi, DSI_DPI_CFG_POL, val);
1258
1259 dsi_write(rk628, dsi, DSI_DPI_VCID, DPI_VID(0));
1260 dsi_write(rk628, dsi, DSI_DPI_LP_CMD_TIM,
1261 OUTVACT_LPCMD_TIME(4) | INVACT_LPCMD_TIME(4));
1262 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL,
1263 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS);
1264
1265 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO)
1266 rk628_dsi_set_vid_mode(rk628, dsi, mode);
1267 else
1268 rk628_dsi_set_cmd_mode(rk628, dsi, mode);
1269
1270 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP);
1271 }
1272
rk628_mipi_dsi_pre_enable(struct rk628 * rk628)1273 void rk628_mipi_dsi_pre_enable(struct rk628 *rk628)
1274 {
1275 struct rk628_dsi *dsi = &rk628->dsi0;
1276 struct rk628_dsi *dsi1 = &rk628->dsi1;
1277 u32 rate = rk628_dsi_get_lane_rate(dsi);
1278 int bus_width;
1279 u32 mask = SW_OUTPUT_MODE_MASK;
1280 u32 val = SW_OUTPUT_MODE(OUTPUT_MODE_DSI);
1281
1282 if (rk628->version == RK628F_VERSION) {
1283 mask = SW_OUTPUT_COMBTX_MODE_MASK;
1284 val = SW_OUTPUT_COMBTX_MODE(OUTPUT_MODE_DSI - 2);
1285
1286 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON3,
1287 GRF_DPHY_CH1_EN_MASK |
1288 GRF_AS_DSIPHY_MASK,
1289 (dsi->slave ? GRF_DPHY_CH1_EN(1) : 0) |
1290 GRF_AS_DSIPHY(1));
1291 }
1292
1293 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, mask, val);
1294 rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON, SW_SPLIT_EN,
1295 dsi->slave ? SW_SPLIT_EN : 0);
1296
1297 bus_width = rate << 8;
1298 if (dsi->slave)
1299 bus_width |= COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
1300 else if (dsi->id)
1301 bus_width |= COMBTXPHY_MODULEB_EN;
1302 else
1303 bus_width |= COMBTXPHY_MODULEA_EN;
1304
1305 rk628_combtxphy_set_bus_width(rk628, bus_width);
1306 rk628_combtxphy_set_mode(rk628, RK628_PHY_MODE_VIDEO_MIPI);
1307 dsi->lane_mbps = rk628_combtxphy_get_bus_width(rk628);
1308
1309 if (dsi->slave && dsi1)
1310 dsi1->lane_mbps = rk628_combtxphy_get_bus_width(rk628);
1311
1312 /* rst for dsi0 */
1313 rk628_dsi0_reset_control_assert(rk628);
1314 udelay(40);
1315 rk628_dsi0_reset_control_deassert(rk628);
1316 udelay(40);
1317
1318 rk628_dsi_bridge_pre_enable(rk628, dsi);
1319
1320 if (dsi->slave) {
1321 /* rst for dsi1 */
1322 rk628_dsi1_reset_control_assert(rk628);
1323 udelay(40);
1324 rk628_dsi1_reset_control_deassert(rk628);
1325 udelay(40);
1326
1327 rk628_dsi_bridge_pre_enable(rk628, dsi1);
1328 }
1329
1330 rk628_panel_prepare(rk628);
1331 panel_simple_xfer_dsi_cmd_seq(rk628, rk628->panel->on_cmds);
1332
1333 #ifdef DSI_READ_POWER_MODE
1334 u8 mode;
1335
1336 rk628_mipi_dsi_dcs_read(rk628, MIPI_DCS_GET_POWER_MODE,
1337 &mode, sizeof(mode));
1338
1339 printf("rk628 dsi: mode: 0x%x\n", mode);
1340 #endif
1341
1342 printf("rk628_dsi final DSI-Link bandwidth: %d x %d\n",
1343 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);
1344 }
1345
rk628_mipi_dsi_enable(struct rk628 * rk628)1346 void rk628_mipi_dsi_enable(struct rk628 *rk628)
1347 {
1348 const struct rk628_dsi *dsi = &rk628->dsi0;
1349 const struct rk628_dsi *dsi1 = &rk628->dsi1;
1350
1351 rk628_dsi_bridge_enable(rk628, dsi);
1352
1353 if (dsi->slave)
1354 rk628_dsi_bridge_enable(rk628, dsi1);
1355
1356 rk628_panel_enable(rk628);
1357 }
1358
rk628_dsi_disable(struct rk628 * rk628)1359 void rk628_dsi_disable(struct rk628 *rk628)
1360 {
1361 const struct rk628_dsi *dsi = &rk628->dsi0;
1362 const struct rk628_dsi *dsi1 = &rk628->dsi1;
1363
1364 rk628_panel_disable(rk628);
1365
1366 dsi_write(rk628, dsi, DSI_PWR_UP, RESET);
1367 dsi_write(rk628, dsi, DSI_LPCLK_CTRL, 0);
1368 dsi_write(rk628, dsi, DSI_EDPI_CMD_SIZE, 0);
1369 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_COMMAND_MODE));
1370 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP);
1371
1372 //dsi_write(rk628, dsi, DSI_PHY_RSTZ, 0);
1373
1374 if (dsi->slave) {
1375 dsi_write(rk628, dsi1, DSI_PWR_UP, RESET);
1376 dsi_write(rk628, dsi1, DSI_LPCLK_CTRL, 0);
1377 dsi_write(rk628, dsi1, DSI_EDPI_CMD_SIZE, 0);
1378 dsi_write(rk628, dsi1, DSI_MODE_CFG,
1379 CMD_VIDEO_MODE(RK628_DSI_COMMAND_MODE));
1380 dsi_write(rk628, dsi1, DSI_PWR_UP, POWER_UP);
1381
1382 //dsi_write(rk628, dsi1, DSI_PHY_RSTZ, 0);
1383 }
1384
1385 panel_simple_xfer_dsi_cmd_seq(rk628, rk628->panel->off_cmds);
1386 rk628_panel_unprepare(rk628);
1387 rk628_combtxphy_power_off(rk628);
1388 }
1389
1390