1 /*
2 * Copyright (c) 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <boot_rkimg.h>
8 #include <cli.h>
9 #include <debug_uart.h>
10 #include <miiphy.h>
11 #include <syscon.h>
12 #include <asm/arch/clock.h>
13 #include <asm/io.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/grf_rv1106.h>
16 #include <asm/arch/ioc_rv1106.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define PERI_GRF_BASE 0xff000000
21 #define PERI_GRF_PERI_CON1 0x0004
22
23 #define CORE_GRF_BASE 0xff040000
24 #define CORE_GRF_CACHE_PERI_ADDR_START 0x0024
25 #define CORE_GRF_CACHE_PERI_ADDR_END 0x0028
26 #define CORE_GRF_MCU_CACHE_MISC 0x002c
27
28 #define PERI_GRF_BASE 0xff000000
29 #define PERI_GRF_USBPHY_CON0 0x0050
30
31 #define PERI_SGRF_BASE 0xff070000
32 #define PERI_SGRF_FIREWALL_CON0 0x0020
33 #define PERI_SGRF_FIREWALL_CON1 0x0024
34 #define PERI_SGRF_FIREWALL_CON2 0x0028
35 #define PERI_SGRF_FIREWALL_CON3 0x002c
36 #define PERI_SGRF_FIREWALL_CON4 0x0030
37 #define PERI_SGRF_SOC_CON3 0x00bc
38
39 #define CORE_SGRF_BASE 0xff076000
40 #define CORE_SGRF_FIREWALL_CON0 0x0020
41 #define CORE_SGRF_FIREWALL_CON1 0x0024
42 #define CORE_SGRF_FIREWALL_CON2 0x0028
43 #define CORE_SGRF_FIREWALL_CON3 0x002c
44 #define CORE_SGRF_FIREWALL_CON4 0x0030
45 #define CORE_SGRF_CPU_CTRL_CON 0x0040
46 #define CORE_SGRF_HPMCU_BOOT_ADDR 0x0044
47
48 #define PMU_SGRF_BASE 0xff080000
49
50 /* QoS Generator Base Address */
51 #define QOS_CPU_BASE 0xff110000
52 #define QOS_CRYPTO_BASE 0xff120000
53 #define QOS_DECOM_BASE 0xff120080
54 #define QOS_DMAC_BASE 0xff120100
55 #define QOS_EMMC_BASE 0xff120180
56 #define QOS_FSPI_BASE 0xff120200
57 #define QOS_IVE_RD_BASE 0xff120280
58 #define QOS_IVE_WR_BASE 0xff120300
59 #define QOS_USB_BASE 0xff120380
60 #define QOS_ISP_BASE 0xff130000
61 #define QOS_SDMMC0_BASE 0xff130080
62 #define QOS_VICAP_BASE 0xff130100
63 #define QOS_NPU_BASE 0xff140000
64 #define QOS_VENC_BASE 0xff150000
65 #define QOS_VEPU_PP_BASE 0xff150080
66 #define QOS_MAC_BASE 0xff160000
67 #define QOS_RGA_RD_BASE 0xff160080
68 #define QOS_RGA_WR_BASE 0xff160100
69 #define QOS_SDIO_BASE 0xff160280
70 #define QOS_VOP_BASE 0xff160300
71
72 #define QOS_PRIORITY 0x0008
73 #define QOS_MODE 0x000c
74 #define QOS_BANDWIDTH 0x0010
75 #define QOS_SATURATION 0x0014
76 #define QOS_EXTCONTROL 0x0018
77
78 /* Shaping Base Address */
79 #define SHAPING_CPU_BASE 0xff110080
80 #define SHAPING_DECOM_BASE 0xff110400
81 #define SHAPING_IVE_RD_BASE 0xff120480
82 #define SHAPING_IVE_WR_BASE 0xff120500
83 #define SHAPING_ISP_BASE 0xff130180
84 #define SHAPING_VICAP_BASE 0xff130200
85 #define SHAPING_NPU_BASE 0xff140080
86 #define SHAPING_VENC_BASE 0xff150100
87 #define SHAPING_VEPU_PP_BASE 0xff150180
88 #define SHAPING_RGA_RD_BASE 0xff160380
89 #define SHAPING_RGA_WR_BASE 0xff160400
90 #define SHAPING_VOP_BASE 0xff160580
91
92 #define SHAPING_NBPKTMAX 0x0008
93
94 #define FW_DDR_BASE 0xff900000
95 #define FW_DDR_MST3_REG 0x4c
96 #define FW_SHRM_BASE 0xff910000
97 #define FW_SHRM_MST1_REG 0x44
98
99 #define PMU_BASE 0xff300000
100 #define PMU_BIU_IDLE_ST 0x00d8
101
102 #define CRU_BASE 0xff3b0000
103 #define CRU_GLB_RST_CON 0x0c10
104 #define CRU_PVTPLL0_CON0_L 0x1000
105 #define CRU_PVTPLL0_CON1_L 0x1008
106 #define CRU_PVTPLL1_CON0_L 0x1030
107 #define CRU_PVTPLL1_CON1_L 0x1038
108
109 #define CORECRU_BASE 0xff3b8000
110 #define CORECRU_CORESOFTRST_CON01 0xa04
111
112 #define USBPHY_APB_BASE 0xff3e0000
113 #define USBPHY_FSLS_DIFF_RECEIVER 0x0100
114
115 #define CSI_PHY_BASE 0xff3e8000
116 #define CSI_DPHY_LANE_EN 0x0
117 #define CSI_DPHY_DUAL_CLK_ENABLE 0x80
118 #define CSI_DPHY_PATH0_MODE 0x44c
119 #define CSI_DPHY_PATH1_MODE 0x84c
120
121 #define GPIO0_IOC_BASE 0xFF388000
122 #define GPIO1_IOC_BASE 0xFF538000
123 #define GPIO2_IOC_BASE 0xFF548000
124 #define GPIO3_IOC_BASE 0xFF558000
125 #define GPIO4_IOC_BASE 0xFF568000
126
127 #define GPIO3A_IOMUX_SEL_L 0x0040
128 #define GPIO3A_IOMUX_SEL_H 0x0044
129
130 #define GPIO4A_IOMUX_SEL_L 0x000
131 #define GPIO4A_IOMUX_SEL_H 0x004
132 #define GPIO4B_IOMUX_SEL_L 0x008
133
134 #define GPIO4_IOC_GPIO4B_DS0 0x0030
135 #define GPIO4_IOC_SARADC_IO_CON 0x00c0
136
137 #define VICRU_BASE 0XFF3B4000
138 #define VICRU_VISOFTRST_CON01 0xA04
139
140 /* OS_REG1[2:0]: chip ver */
141 #define CHIP_VER_REG 0xff020204
142 #define CHIP_VER_MSK 0x7
143 #define V(x) ((x) - 1)
144 #define ROM_VER_REG 0xffff4ffc
145 #define ROM_V2 0x30303256
146
147 /* uart0 iomux */
148 /* gpio0a0 */
149 #define UART0_RX_M0 1
150 #define UART0_RX_M0_OFFSET 0
151 #define UART0_RX_M0_ADDR (GPIO1_IOC_BASE)
152 /* gpio0a1 */
153 #define UART0_TX_M0 1
154 #define UART0_TX_M0_OFFSET 4
155 #define UART0_TX_M0_ADDR (GPIO1_IOC_BASE)
156
157 /* gpio2b0 */
158 #define UART0_RX_M1 1
159 #define UART0_RX_M1_OFFSET 0
160 #define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x28)
161 /* gpio2b1 */
162 #define UART0_TX_M1 1
163 #define UART0_TX_M1_OFFSET 4
164 #define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x28)
165
166 /* gpio4a0 */
167 #define UART0_RX_M2 3
168 #define UART0_RX_M2_OFFSET 0
169 #define UART0_RX_M2_ADDR (GPIO4_IOC_BASE)
170 /* gpio4a1 */
171 #define UART0_TX_M2 3
172 #define UART0_TX_M2_OFFSET 4
173 #define UART0_TX_M2_ADDR (GPIO4_IOC_BASE)
174
175 /* uart1 iomux */
176 /* gpio1a4 */
177 #define UART1_RX_M0 1
178 #define UART1_RX_M0_OFFSET 0
179 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x4)
180 /* gpio1a3 */
181 #define UART1_TX_M0 1
182 #define UART1_TX_M0_OFFSET 12
183 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE)
184
185 /* gpio2a5 */
186 #define UART1_RX_M1 4
187 #define UART1_RX_M1_OFFSET 4
188 #define UART1_RX_M1_ADDR (GPIO2_IOC_BASE + 0x24)
189 /* gpio2a4 */
190 #define UART1_TX_M1 4
191 #define UART1_TX_M1_OFFSET 0
192 #define UART1_TX_M1_ADDR (GPIO2_IOC_BASE + 0x24)
193
194 /* gpio4a7 */
195 #define UART1_RX_M2 3
196 #define UART1_RX_M2_OFFSET 12
197 #define UART1_RX_M2_ADDR (GPIO4_IOC_BASE + 0x4)
198 /* gpio4a5 */
199 #define UART1_TX_M2 3
200 #define UART1_TX_M2_OFFSET 4
201 #define UART1_TX_M2_ADDR (GPIO4_IOC_BASE + 0x4)
202
203 /* uart2 iomux */
204 /* gpio3a3 */
205 #define UART2_RX_M0 2
206 #define UART2_RX_M0_OFFSET 12
207 #define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x40)
208 /* gpio3a2 */
209 #define UART2_TX_M0 2
210 #define UART2_TX_M0_OFFSET 8
211 #define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x40)
212
213 /* gpio1b3 */
214 #define UART2_RX_M1 2
215 #define UART2_RX_M1_OFFSET 12
216 #define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x8)
217 /* gpio1b2 */
218 #define UART2_TX_M1 2
219 #define UART2_TX_M1_OFFSET 8
220 #define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x8)
221
222 /* uart3 iomux */
223 /* gpio1a1 */
224 #define UART3_RX_M0 1
225 #define UART3_RX_M0_OFFSET 4
226 #define UART3_RX_M0_ADDR (GPIO1_IOC_BASE)
227 /* gpio1a0 */
228 #define UART3_TX_M0 1
229 #define UART3_TX_M0_OFFSET 0
230 #define UART3_TX_M0_ADDR (GPIO1_IOC_BASE)
231
232 /* gpio1d1 */
233 #define UART3_RX_M1 5
234 #define UART3_RX_M1_OFFSET 4
235 #define UART3_RX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
236 /* gpio1d0 */
237 #define UART3_TX_M1 5
238 #define UART3_TX_M1_OFFSET 0
239 #define UART3_TX_M1_ADDR (GPIO2_IOC_BASE + 0x18)
240
241 /* uart4 iomux */
242 /* gpio1b0 */
243 #define UART4_RX_M0 1
244 #define UART4_RX_M0_OFFSET 0
245 #define UART4_RX_M0_ADDR (GPIO1_IOC_BASE + 0x8)
246 /* gpio1b1 */
247 #define UART4_TX_M0 1
248 #define UART4_TX_M0_OFFSET 4
249 #define UART4_TX_M0_ADDR (GPIO1_IOC_BASE + 0x8)
250
251 /* gpio1c4 */
252 #define UART4_RX_M1 4
253 #define UART4_RX_M1_OFFSET 0
254 #define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x14)
255 /* gpio1c5 */
256 #define UART4_TX_M1 4
257 #define UART4_TX_M1_OFFSET 4
258 #define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x14)
259
260 /* uart5 iomux */
261 /* gpio3a7 */
262 #define UART5_RX_M0 2
263 #define UART5_RX_M0_OFFSET 11
264 #define UART5_RX_M0_ADDR (GPIO3_IOC_BASE + 0x44)
265 /* gpio3a6 */
266 #define UART5_TX_M0 1
267 #define UART5_TX_M0_OFFSET 8
268 #define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x44)
269
270 /* gpio1d2 */
271 #define UART5_RX_M1 4
272 #define UART5_RX_M1_OFFSET 8
273 #define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
274 /* gpio1d3 */
275 #define UART5_TX_M1 4
276 #define UART5_TX_M1_OFFSET 12
277 #define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x18)
278
279 /* gpio3d0 */
280 #define UART5_RX_M2 2
281 #define UART5_RX_M2_OFFSET 0
282 #define UART5_RX_M2_ADDR (GPIO3_IOC_BASE + 0x58)
283 /* gpio3c7 */
284 #define UART5_TX_M2 2
285 #define UART5_TX_M2_OFFSET 12
286 #define UART5_TX_M2_ADDR (GPIO4_IOC_BASE + 0x54)
287
288 #define set_uart_iomux(bits_offset, bits_val, addr) \
289 writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
290
291 #define set_uart_iomux_rx(ID, MODE) \
292 set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
293 #define set_uart_iomux_tx(ID, MODE) \
294 set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
295
board_debug_uart_init(void)296 void board_debug_uart_init(void)
297 {
298 /* UART 0 */
299 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4a0000)
300
301 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
302 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
303
304 /* UART0_M0 Switch iomux */
305 set_uart_iomux_rx(0, 0);
306 set_uart_iomux_tx(0, 0);
307 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
308 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
309
310 /* UART0_M1 Switch iomux */
311 set_uart_iomux_rx(0, 1);
312 set_uart_iomux_tx(0, 1);
313 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
314 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
315
316 /* UART0_M2 Switch iomux */
317 set_uart_iomux_rx(0, 2);
318 set_uart_iomux_tx(0, 2);
319 #endif
320
321 /* UART 1 */
322 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4b0000)
323
324 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
325 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
326
327 /* UART1_M0 Switch iomux */
328 set_uart_iomux_rx(1, 0);
329 set_uart_iomux_tx(1, 0);
330 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
331 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
332
333 /* UART1_M1 Switch iomux */
334 set_uart_iomux_rx(1, 1);
335 set_uart_iomux_tx(1, 1);
336 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
337 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
338
339 /* UART1_M2 Switch iomux */
340 set_uart_iomux_rx(1, 2);
341 set_uart_iomux_tx(1, 2);
342 #endif
343 /* UART 2 */
344 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4c0000)
345
346 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
347 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
348
349 /* UART2_M0 Switch iomux */
350 set_uart_iomux_rx(2, 0);
351 set_uart_iomux_tx(2, 0);
352 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
353 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
354
355 /* UART2_M1 Switch iomux */
356 set_uart_iomux_rx(2, 1);
357 set_uart_iomux_tx(2, 1);
358 #endif
359
360 /* UART 3 */
361 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4d0000)
362 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
363 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
364
365 /* UART3_M0 Switch iomux */
366 set_uart_iomux_rx(3, 0);
367 set_uart_iomux_tx(3, 0);
368 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
369 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
370
371 /* UART3_M1 Switch iomux */
372 set_uart_iomux_rx(3, 1);
373 set_uart_iomux_tx(3, 1);
374 #endif
375 /* UART 4 */
376 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4e0000)
377 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
378 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
379
380 /* UART4_M0 Switch iomux */
381 set_uart_iomux_rx(4, 0);
382 set_uart_iomux_tx(4, 0);
383 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
384 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
385
386 /* UART4_M1 Switch iomux */
387 set_uart_iomux_rx(4, 1);
388 set_uart_iomux_tx(4, 1);
389 #endif
390 /* UART 5 */
391 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4f0000)
392 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
393 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
394
395 /* UART5_M0 Switch iomux */
396 set_uart_iomux_rx(5, 0);
397 set_uart_iomux_tx(5, 0);
398 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
399 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
400
401 /* UART5_M1 Switch iomux */
402 set_uart_iomux_rx(5, 1);
403 set_uart_iomux_tx(5, 1);
404 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
405 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
406
407 /* UART5_M2 Switch iomux */
408 set_uart_iomux_rx(5, 2);
409 set_uart_iomux_tx(5, 2);
410 #endif
411 #endif
412 }
413
414 #ifdef CONFIG_SUPPORT_USBPLUG
board_set_iomux(enum if_type if_type,int devnum,int routing)415 void board_set_iomux(enum if_type if_type, int devnum, int routing)
416 {
417 switch (if_type) {
418 case IF_TYPE_MMC:
419 /* emmc iomux */
420 writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
421 writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
422 writel(0x00ff0011, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
423 break;
424 case IF_TYPE_MTD:
425 /* fspi iomux */
426 writel(0x0f000700, GPIO4_IOC_BASE + 0x0030);
427 writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
428 writel(0x0f0f0202, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
429 writel(0x00ff0022, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
430 break;
431 default:
432 break;
433 }
434 }
435 #endif
436
arch_cpu_init(void)437 int arch_cpu_init(void)
438 {
439 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
440 /* Save chip version to OS_REG1[2:0] */
441 if (readl(ROM_VER_REG) == ROM_V2)
442 writel((readl(CHIP_VER_REG) & ~CHIP_VER_MSK) | V(2), CHIP_VER_REG);
443 else
444 writel((readl(CHIP_VER_REG) & ~CHIP_VER_MSK) | V(1), CHIP_VER_REG);
445
446 /* Set all devices to Non-secure */
447 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON0);
448 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON1);
449 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON2);
450 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON3);
451 writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON4);
452 writel(0x000f0000, PERI_SGRF_BASE + PERI_SGRF_SOC_CON3);
453 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON0);
454 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON1);
455 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON2);
456 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON3);
457 writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON4);
458 writel(0x00030002, CORE_SGRF_BASE + CORE_SGRF_CPU_CTRL_CON);
459 writel(0x20000000, PMU_SGRF_BASE);
460
461 /* Set the emmc and fspi to access secure area */
462 writel(0x00000000, FW_DDR_BASE + FW_DDR_MST3_REG);
463 writel(0xff00ffff, FW_SHRM_BASE + FW_SHRM_MST1_REG);
464
465 /* Set fspi clk 6mA */
466 if ((readl(GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L) & 0x70) == 0x20)
467 writel(0x3f000700, GPIO4_IOC_BASE + GPIO4_IOC_GPIO4B_DS0);
468
469 /*
470 * Set the USB2 PHY in suspend mode and turn off the
471 * USB2 PHY FS/LS differential receiver to save power:
472 * VCC1V8_USB : reduce 3.8 mA
473 * VDD_0V9 : reduce 4.4 mA
474 */
475 writel(0x01ff01d1, PERI_GRF_BASE + PERI_GRF_USBPHY_CON0);
476 writel(0x00000000, USBPHY_APB_BASE + USBPHY_FSLS_DIFF_RECEIVER);
477
478 /* release the wdt */
479 writel(0x2000200, PERI_GRF_BASE + PERI_GRF_PERI_CON1);
480
481 /*
482 * enable tsadc trigger global reset and select first reset.
483 * enable wdt trigger global/pmu reset and select first reset.
484 * select first reset trigger pmu reset.
485 */
486 writel(0x85f, CRU_BASE + CRU_GLB_RST_CON);
487
488 /*
489 * When venc/npu use pvtpll, reboot will fail, because
490 * pvtpll is reset before venc/npu reset, so venc/npu
491 * is not completely reset, system will block when access
492 * NoC in SPL.
493 * Enable pvtpll can make venc/npu reset go on, wait
494 * until venc/npu is reset completely.
495 */
496 writel(0xffff0018, CRU_BASE + CRU_PVTPLL0_CON1_L);
497 writel(0x00030003, CRU_BASE + CRU_PVTPLL0_CON0_L);
498 writel(0xffff0018, CRU_BASE + CRU_PVTPLL1_CON1_L);
499 writel(0x00030003, CRU_BASE + CRU_PVTPLL1_CON0_L);
500 udelay(2);
501
502 if (readl(PMU_BASE + PMU_BIU_IDLE_ST)) {
503 printascii("BAD PMU_BIU_IDLE_ST: ");
504 printhex8(readl(PMU_BASE + PMU_BIU_IDLE_ST));
505 }
506
507 /*
508 * Limits npu max transport packets to 4 for route to scheduler,
509 * give much more chance for other controllers to access memory.
510 * such as VENC.
511 */
512 writel(0x4, SHAPING_NPU_BASE + SHAPING_NBPKTMAX);
513
514 /* Improve VENC QOS PRIORITY */
515 writel(0x303, QOS_VENC_BASE + QOS_PRIORITY);
516
517 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY
518 /* Pinctrl is disabled, set sdmmc0 iomux here */
519 writel(0xfff01110, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L);
520 writel(0xffff1111, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H);
521 #endif
522
523 #if defined(CONFIG_ROCKCHIP_SFC_IOMUX)
524 /* fspi iomux */
525 writel(0x0f000700, GPIO4_IOC_BASE + 0x0030);
526 writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
527 writel(0x0f0f0202, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
528 writel(0x00ff0022, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
529 #elif defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
530 /* emmc iomux */
531 writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
532 writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
533 writel(0x00ff0011, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
534 #endif
535
536 /* Set GPIO3_B0~GPIO3B7 and GPIO3_C0~GPIO3_C3 of MIPI CSI DPHY to default GPIO Input 1V8 Only mode */
537 writel(0x0000007d, CSI_PHY_BASE + CSI_DPHY_LANE_EN);
538 writel(0x0000005f, CSI_PHY_BASE + CSI_DPHY_DUAL_CLK_ENABLE);
539 writel(0x00000001, CSI_PHY_BASE + CSI_DPHY_PATH0_MODE);
540 writel(0x00000001, CSI_PHY_BASE + CSI_DPHY_PATH1_MODE);
541 /* Set GPIO4_C0 GPIO4C1 of SARADC to default GPIO Input 1V8 Only mode */
542 writel(0x000c000c, GPIO4_IOC_BASE + GPIO4_IOC_SARADC_IO_CON);
543
544 #endif
545 /* reset sdmmc0 to prevent power leak */
546 writel(0x30003000, VICRU_BASE + VICRU_VISOFTRST_CON01);
547 udelay(1);
548 writel(0x30000000, VICRU_BASE + VICRU_VISOFTRST_CON01);
549
550 return 0;
551 }
552
553 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)554 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
555 {
556 if (!strcmp(id, "mcu0")) {
557 /* set the mcu uncache area, usually set the devices address */
558 writel(0xff000, CORE_GRF_BASE + CORE_GRF_CACHE_PERI_ADDR_START);
559 writel(0xffc00, CORE_GRF_BASE + CORE_GRF_CACHE_PERI_ADDR_END);
560 /* Reset the hp mcu */
561 writel(0x1e001e, CORECRU_BASE + CORECRU_CORESOFTRST_CON01);
562 /* set the mcu addr */
563 writel(entry_point, CORE_SGRF_BASE + CORE_SGRF_HPMCU_BOOT_ADDR);
564 /* release the mcu */
565 writel(0x1e0000, CORECRU_BASE + CORECRU_CORESOFTRST_CON01);
566 } else if (!strcmp(id, "mcu1")) {
567 /* set the mcu addr */
568 writel(entry_point, CORE_SGRF_BASE + CORE_SGRF_HPMCU_BOOT_ADDR);
569 }
570
571 return 0;
572 }
573
rk_meta_process(void)574 void rk_meta_process(void)
575 {
576 writel(0x00080008, CORE_GRF_BASE + CORE_GRF_MCU_CACHE_MISC);
577 }
578 #endif
579
580 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY
rk_board_scan_bootdev(void)581 int rk_board_scan_bootdev(void)
582 {
583 char *devtype, *devnum;
584
585 if (!run_command("blk dev mmc 1", 0) &&
586 !run_command("rkimgtest mmc 1", 0)) {
587 devtype = "mmc";
588 devnum = "1";
589 } else {
590 run_command("blk dev mtd 2", 0);
591 devtype = "mtd";
592 devnum = "2";
593 }
594 env_set("devtype", devtype);
595 env_set("devnum", devnum);
596
597 return 0;
598 }
599 #endif
600
601 #if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
602 #define GMAC_NODE_FDT_PATH "/ethernet@ffa80000"
603 #define RK630_MII_NAME "ethernet@ffa80000"
604 #define PHY_ADDR 2
605 #define PAGE_SWITCH 0x1f
606 #define DISABLE_APS_REG 0x12
607 #define DISABLE_APS_VAL 0x4824
608 #define PHYAFE_PDCW_REG 0x1c
609 #define PHYAFE_PDCW_VAL 0x8880
610 #define PD_ANALOG_REG 0x0
611 #define PD_ANALOG_VAL 0x3900
612 #define RV1106_MACPHY_SHUTDOWN BIT(1)
613 #define RV1106_MACPHY_ENABLE_MASK BIT(1)
614
rk_board_fdt_pwrdn_gmac(const void * blob)615 static int rk_board_fdt_pwrdn_gmac(const void *blob)
616 {
617 void *fdt = (void *)gd->fdt_blob;
618 struct rv1106_grf *grf;
619 int gmac_node;
620
621 /* Turn off GMAC FEPHY to reduce chip power consumption at uboot level,
622 * if the gmac node is disabled at kernel dtb. RV1106/1103 has the
623 * internal gmac phy, u-boot.dtb defines and enables the gmac node
624 * by default, so even if the gmac node of the kernel dts is disabled,
625 * U-Boot will enable and initialize the gmac phy. So it is not okay
626 * to turn off gmac phy by default in arch_cpu_init(), need to turn off
627 * gmac phy in the current function.
628 */
629 gmac_node = fdt_path_offset(gd->fdt_blob, GMAC_NODE_FDT_PATH);
630 if (fdt_stringlist_search(fdt, gmac_node, "status", "disabled") >= 0) {
631 /* switch to page 1 */
632 miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0100);
633 miiphy_write(RK630_MII_NAME, PHY_ADDR, DISABLE_APS_REG,
634 DISABLE_APS_VAL);
635 /* switch to pae 6 */
636 miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0600);
637 miiphy_write(RK630_MII_NAME, PHY_ADDR, PHYAFE_PDCW_REG,
638 PHYAFE_PDCW_VAL);
639 /* switch to page 0 */
640 miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0000);
641 miiphy_write(RK630_MII_NAME, PHY_ADDR, PD_ANALOG_REG,
642 PD_ANALOG_VAL);
643
644 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
645 if (grf)
646 rk_clrsetreg(&grf->macphy_con0,
647 RV1106_MACPHY_ENABLE_MASK,
648 RV1106_MACPHY_SHUTDOWN);
649 }
650
651 return 0;
652 }
653 #endif
654
rk_board_fdt_fixup(const void * blob)655 int rk_board_fdt_fixup(const void *blob)
656 {
657 #if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
658 rk_board_fdt_pwrdn_gmac(blob);
659 #endif
660
661 return 0;
662 }
663